Sharp UX-B800A, Руководство по обслуживанию, Страница: 80 / 140

UX-B800A
5 – 10
PIN NO. NAME SYMBOL BUFFER
TYPE
DESCRIPTION
TQFP QFP
3-5 5-7 I/O Base IOS0-IOS2 I with pul-
lup**
Input. External switches can be connected to these
lines to select between predefined EEPROM config-
urations.
6 8 Enable EEPROM ENEEP I with pul-
lup**
Input. Enables (when high or open) LAN91C113
accesses to the serial EEPROM. Must be grounded
if no EEPROM is connected to the LAN91C113.
127, 128 1, 2 Crystal 1
Crystal 2 XTAL1
XTAL2 Iclk An external 25 MHz crystal is connected across
these pins. If a TTL clock is supplied instead, it
should be connected to XTAL1 and XTAL2 should be
left open.
1, 33, 44, 62, 77,
98, 110, 120, 96,
97 3, 35, 46, 64, 79,
100, 112, 122, 98,
99 Power VDD - +3.3V Power supply pins.
11, 16 13, 18 Analog Power AVDD - +3.3V Analog power supply pins.
24, 39, 52, 57, 67,
72, 93, 103, 108,
117 26, 41, 54, 59, 69,
74, 95, 105, 110,
119 Ground GND - Ground pins.
13, 19 15, 21 Analog Ground AGND - Analog Ground pins
21 23 Loopback O4 - Output. Active when LOOP bit is set (TCR bit 1).
20 22 nLink Status nLNK I with pullup Input General-purpose input port used to convey
LINK status (EPHSR bit 14).
28 30 nCNTRL nCNTRL O12 General Purpose Control Pin
47 49 X25out X25out O12 25Mhz Output to external PHY
111 113 Transmit Enable
100 Mbps
TXEN100 O12 Output to MII PHY. Envelope to 100 Mbps transmis-
sion.
119 121 Carrier Sense
100 Mbps
CRS100 I with pull-
down
Input from MII PHY. Envelope of packet reception
used for deferral and backoff purposes.
125 127 Receive Data
Valid
RX_DV I with pull-
down
Input from MII PHY. Envelope of data valid reception.
Used for receive data framing.
112 114 Collision Detect
100 Mbps
COL100 I with pull-
down
Input from MII PHY. Collision detection input.
113-116 115-118 Transmit Data TXD3-TXD0 O12 Outputs. Transmit Data nibble to MII PHY.
109 111 Transmit Clock TX25 I with pullup Input. Transmit clock input from MII. Nibble rale
clock (25MHz for 100Mbps & 2.5MHz for 10Mbps).
118 120 Receive Clock RX25 I with pullup Input. Receive clock input from MII PHY. Nibble rate
clock. (25MHz for 100Mbps & 2.5MHz for 10Mbps).
121-124 123-126 Receive Data RXD3-RXD0 I with pullup Inputs. Received Data nibble from MII PHY.
25 27 Management
Data Input
MDI I with pull-
down
MII management data input.
26 28 Management
Data Output
MDO O4 MII management data output.
27 29 Management
Clock
MCLK O4 MII management clock.
126 128 Receive Error RX_ER I with pull-
down
Input. Indicates a code error detected by PHY. Used
by the LAN91C113 to discard the packet being
received. The error indication reported for this event
is the same as a bad CRC (Receive Status Word bit
13).
2 4 nChip Select Out-
put
nCSOUT O4 Output. Chip Select provided for mapping of PHY
functions into LAN91C113 decoded space. Active on
accesses to LAN91C113's eight lower addresses
when the BANK SELECTED is 7.
12 14 External Resistor RBIAS NA Transmit Current Set. An external resistor connected
between this pin and GND will set the output current
for the TP transmit outputs.
14 16 - TPO+ O/I Twisted Pair Transmit Output, Positive.
15 17 - TPO- O/I Twisted Pair Transmit Output, Negative.
17 19 - TPI+ I/O Twisted Pair Receive Input, Positive.
18 20 - TPI- I/O Twisted Pair Receive Input, Negative.
22 24 - nLEDA OD24 PHY LED Output
23 25 - nLEDB OD24 PHY LED Output
34,48-51,53-
56,58-61,63-66 36,50-53,55-
58,60-63,65-68 - NC - No Connection