Sharp UX-B800A, Руководство по обслуживанию, Страница: 78 / 140

UX-B800A
5 – 8
3) A/D converter
The ADC input provides a 0/-4 dBm low pass filter. The ADC is a second order sigma-delta type ADC which samples at a rate between 1.024 MHz
and 2.048 MHz to produce a programmable baseband sample, depending on the decimation ratio programmed in the decimation filter and the clock
value.
4) D/A converter
The incoming digital signal from the MDP is fed to a low pass interpolation filter and then to a second order delta-sigma type DAC. The DAC analog
output drivers a switched capacitor analog filter. The output of this filter is passed to a passive continuous-time second order low pass filter that
removes signal images around the switched capacitor clock frequency.
5) Speaker output
The SPKR_OUT output signal can drive a 150
Ω
resistive load. The speaker driver is intended to buffer and drive the low impedance speaker load
with the signal selected on its input. The microphone input, or the line input, or the transmit output signal can be selected to be the speaker output.
The speaker driver output can be attenuated or muted. It also has power down mode.
6) Line output
The main purpose of the line output stage is to buffer the signal and drive the low impedance line load with the signal selected on its input. The micro-
phone input, or the line input, or the transmit output signal can be selected to be the line output. The line drive provides a 600
Ω
differential output.
7) Power up condition
Upon application of the both AVDD and VDD power, the power up sequence consists of:
1. the internal reset circuit becoming activated.
2. The VREF and VC generators powering up.
This power-on sequence takes approximately 50ms.
2.4. IC702 (LAN91C113) Hardware description
2.4.1 General description
The SMSC LAN91C113 is designed to facilitate the implementation of a third generation of Fast Ethernet connectivity solutions for embedded appli-
cations. For this third generation of products, flexibility and integration dominate the design requirements. The LAN91C113 is a mixed signal Analog/
Digital device that implements the MAC and PHY portion of the CSMA/CD protocol at 10 and 100 Mbps. The design will also minimize data through-
put constraints utilizing a 16-bit or 8-bit bus Host interface in embedded applications.
The total internal memory FIFO buffer size is 8 Kbytes, which is the total chip storage for transmit and receive operations.
The SMSC LAN91C113 is software compatible with the LAN9000 family of products.
Memory management is handled using a patented optimized MMU (Memory Management Unit) architecture and a 16-bit wide internal data path. This
I/O mapped architecture can sustain back-to-back frame transmission and reception for superior data throughput and optimal performance. It also
dynamically allocates buffer memory in an efficient buffer utilization scheme, reducing software tasks and relieving the host CPU from performing
these housekeeping functions.
The SMSC 91C113 provides a flexible slave interface for easy connectivity with industry-standard buses. The Bus Interface Unit (BIU) can handle
synchronous as well as asynchronous transfers, with different signals being used for each one. Asynchronous bus support for ISA is supported even
though ISA cannot sustain 100 Mbps traffic. Fast Ethernet data rates are attainable for ISA-based nodes on the basis of the aggregate traffic benefits.
Two different interfaces are supported on the network side. The first Interface is a standard Magnetics transmit/receive pair interfacing to 10/100Base-
T utilizing the internal physical layer block. The second interface follows the MII (Media Independent Interface) specification standard, consisting of 4
bit wide data transfers at the nibble rate. This interface is applicable to 10 Mbps standard Ethernet or 100 Mbps Ethernet networks. Three of the
LAN91C113's pins are used to interface to the two-line MII serial management protocol.
The SMSC LAN91C113 integrates IEEE 802.3 Physical Layer for twisted pair Ethernet applications. The PHY can be configured for either 100 Mbps
(100Base-TX) or 10 Mbps (10Base-T) Ethernet operation. The Analog PHY block consists of a 4B5B>Manchester encoder/decoder, scrambler/de-
scrambler, transmitter with wave shaping and output driver, twisted pair receiver with on chip equalizer and baseline wander correction, clock and
data recovery, Auto-Negotiation, controller interface (MII), and serial port (MI). Internal output wave shaping circuitry and on-chip filters eliminate the
need for external filters normally required in 100Base-TX and 10Base-T applications.
The LAN91C113 can automatically configure itself for 100 or 10 Mbps and Full or Half Duplex operation with the on-chip Auto-Negotiation algorithm.
The LAN91C113 is ideal for media interfaces for embedded application desiring Ethernet connectivity as well as 100Base-TX/10Base-T adapter
cards, motherboards, repeaters, switching hubs. The LAN91C113 operates from a single 3.3V supply. The inputs and outputs of the host interface are
5V tolerant and will directly interface to other 5V devices.
2.4.2 Description of pin functions
IC702: VHILN91C113-1 (LAN91C113)
PIN NO. NAME SYMBOL BUFFER
TYPE
DESCRIPTION
TQFP QFP
81-92 83-94 Address A4-A15 I** Input. Decoded by LAN91C113 to determine access
to its registers.
78-80 80-82 Address A1-A3 I** Input. Used by LAN91C113 for internal register
selection.
41 43 Address Enable AEN I** Input. Used as an address qualifier. Address decod-
ing is only enabled when AEN is low.