Sharp FO-5700, Руководство по обслуживанию, Страница: 47 / 140

FO-5700U
5 – 3
SH7021 (IC27) Terminal descriptions
Classification Code
Terminal No.
I/O Name Function
(TFP-100B)
Bus control WAIT 54 I Wait It is input to insert Tw into the bus cycle during access to the
external space.
RAS 52 O Low address strobe Timing signal of low address strobe of DRAM
CASH 47 O High-order column Timing signal of column address strobe of DRAM
address strobe It is output for access to high-order 8 bits of data.
CASL 49 O Low-order column Timing signal of column address strobe of DRAM
address strobe It is output for access to low-order 8 bits of data.
RD 57 O Read It indicates that outside is read out.
WRH 56 O High-order write It indicates writing at the external high-order 8 bits.
WRL 55 O Low-order write It indicates writing at the external low-order 8 bits.
CS0~CS7 46~49, O Chip select 0 thru 7 Chip select signal for external memory or device
51~54
AH 61 O Address hold Address hold timing signal for device which uses multiplex bus of
address/data
HBS, 20 O Low-/high-order byte Strobe signal of high/low byte
LBS 56 strobe (Commonly used with AO, WRH.)
WR 55 O Write Output during writing. (Commonly used with WRL.)
DMAC DREQ0, 66,68 I DMA transfer request Input terminal of DMA transfer request from external
DREQ1 (Channels 0 and 1)
DACK0, 65,67 O DMA transfer request It indicates that DMA transfer request is received.
DACK1 receiving (Channels
0 and 1)
16-bit TIOCA0, 51, I/O ITU input Output terminal of input capture input/output conveyor
integrated TIOCB0 53 capture/output
timer pulse unit conveyor (Channel 0)
(ITU)
TIOCA1, 62, I/O ITU input Output terminal of input capture input/output conveyor
TIOCB1 64 capture/output
conveyor (Channel 1)
TIOCA2, 83, I/O ITU input Output terminal of input capture input/output conveyor
TIOCB2 84 capture/output
conveyor (Channel 2)
TIOCA3, 85, I/O ITU input Output terminal of input capture input/output conveyor
TIOCB3 86 capture/output
conveyor (Channel 3)
TIOCA4, 87, I/O ITU input Output terminal of input capture input/output conveyor
TIOCB4 89 capture/output
conveyor (Channel 4)
TOCXA4, 90, O ITU output conveyor Output terminal of output conveyor
TOCXB4 91 (Channel 4)
TCLKA~ 65,66,90, I ITU timer clock input External clock input terminal to counter of ITU
TCLKD 91
Timing pattern TP15~ 100~93, O Timing pattern Output terminal of timing pattern
controller (TPC) TP0 91~89, Output 15 thru 0
87~83
Serial TxD0, 94, O Sending data Sending data output terminal of SCI0, 1
communication TxD1 96 (Channels 0 and 1
nterface (SCI)
RxD0, 93, I Receiving data Receiving data input terminal of SCI0, 1
RxD1 95 (Channels 0 and 1)
SCK0, 97, I/O Serial clock Clock input/output terminal of SCI0, 1
SCK1 98 (Channels 0 and 1)
I/O port PA15~ 68~64, I/O Port A Input/output terminal of 16 bits
PA0 62~60, Input/output can be assigned for each bit.
58~51
PB15~ 100~93, I/O Port B Input/output terminal of 16 bits
PB0 91~89, Input/output can be assigned for each bit.
87~83