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User Manual
T201DCH50/100/300/600-MU
ALL RIGHTS RESERVED. NO PART OF THIS PUBLICATION MAY
BE REPRODUCED WITHOUT PRIOR PERMISSION.
www.seneca.it
Doc. MI00546-EN
Rev.2 Page 14
For example, if register 40064 contains the 16 most significant bits (MSW) while register 40065 contains the
least significant 16 bits (LSW), the 32-bit value is obtained by composing the 2 registers:
BIT
15
BIT
14
BIT
13
BIT
12
BIT
11
BIT
10
BIT
9
BIT
8
BIT
7
BIT
6
BIT
5
BIT
4
BIT
3
BIT
2
BIT
1
BIT
0
40064 MOST SIGNIFICANT WORD
BIT
15
BIT
14
BIT
13
BIT
12
BIT
11
BIT
10
BIT
9
BIT
8
BIT
7
BIT
6
BIT
5
BIT
4
BIT
3
BIT
2
BIT
1
BIT
0
40065 LEAST SIGNIFICANT WORD
𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑒𝑒
32𝑏𝑏𝑏𝑏𝑏𝑏
= 𝑅𝑅𝑒𝑒𝑅𝑅𝑅𝑅𝑅𝑅𝑅𝑅𝑒𝑒𝑟𝑟
𝐿𝐿𝐿𝐿𝐿𝐿
+ ( 𝑅𝑅𝑒𝑒𝑅𝑅𝑅𝑅𝑅𝑅𝑅𝑅𝑒𝑒𝑟𝑟
𝑀𝑀𝐿𝐿𝐿𝐿
∗ 65536)
In the reading registers it is possible to swap the most significant word with the least significant word, therefore
it is possible to obtain 40064 as LSW and 40065 as MSW.
5.5.
TYPE OF 32-BIT FLOATING POINT DATA (IEEE 754)
The IEEE 754 standard ( https://en.wikipedia.org/wiki/IEEE_754) defines the format for representing
floating
point numbers.
As already mentioned, since it is a 32-bit data type, its representation occupies two 16-bit holding registers.
To obtain a binary / hexadecimal conversion of a floating point value it is possible to refer to an online
converter at this address:
http://www.h-schmidt.net/FloatConverter/IEEE754.html
Using the last representation the value 2.54 is represented at 32 bits as:
0x40228F5C
Since we have 16-bit registers available, the value must be divided into MSW and LSW:
0x4022 (16418 decimal) are the 16 most significant bits (MSW) while 0x8F5C (36700 decimal) are the 16 least
significant bits (LSW).