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RTC – 4553AC

 

 

 

Page - 4 

MQ - 342 - 01

 

 

7. Electrical characteristics 

 

7.1. DC, AC Characteristics 

 
7.1.1. V

DD

 = 5 V 

 

(1) DC Characteristics 

( GND=0 V , Ta = 

30 

°

 +70 

°

C ) 

V

DD

 = 5 V ± 10 % 

Item Symbol 

Condition 

Min. Typ. Max. 

Unit 

Data retention 

voltage 

V

DH

 

— 

2.0 — 5.5  V 

I

DD

(normal operation) 

SCK   = 500 kHz 

CS0  = L,  CS1 = H 

— — 100 

Current 

consumption 

I

DD

(backup 

operation) 

SCK   = 0 Hz 

CS0  = H,  CS1 = L 

— 1.0 3.0 

µ

V

OH

 

I

OH

 = 

400 

µ

V

DD

 

 

0.4 

— — 

Output voltage 

V

OL

 

I

OL

 = 1.6 mA 

— 

— 

0.4 

I

OZH

 

V

OUT

 = 5.5 V 

2.0 

— 2.0 

Output leak 

current 

I

OZL

 

V

OUT

 = 0 V 

2.0 

— 2.0 

µ

V

IH

 — 

4/5 

V

DD

 — 

— 

Input voltage 

V

IL

 — 

— 

— 

1/5 

V

DD

 

I

IH

 

V

IN

 = 5.5 V 

2.0 

— 2.0 

Input current 

I

IL

 

V

IN

 = 0 V 

2.0 

— 2.0 

µ

Oscillation  

startup time 

Ts 

Ta = +25 °C 

— 

— 

3.0 

 

(2) AC Characteristics 

( GND=0 V , Ta = 

30 

°

 +70 

°

C ) 

V

DD

 = 5 V ± 10 % 

Item

 

Symbol

 

Condition

 

Min. Typ. Max. 

Unit

 

SCK  frequency 

f

CLK

 —  — 

— 

500 

kHz 

SCK  "L" time 

t

WCKL

 —  1.0 

— 

— 

SCK  "H" time 

t

WCKH

 —  1.0 

— 

— 

SCK  pause time 

t

PS

 — 1.0 

— 

— 

CS0  setup time 

t

SCS

 —  0 

— 

— 

CS0  hold time 

t

HCS

 —  0.5 

— 

— 

S

IN 

data setup time 

t

SD

 — 0.2 

— 

— 

S

IN

 data hold time 

t

HD

 — 0.2 

— 

— 

WR  setup time 

t

SWR

 —  1.0 

— 

— 

WR  hold time 

t

HWR

 —  0.5 

— 

— 

µ

S

OUT

 delay time 

t

DS

0 CL=100 

pF  — 

150 

500 

Time lag between  CS0 , CS1 enable 

and S

OUT

 output 

t

DSZ

1 CL=100 

pF  — — 100 

Time lag between  CS0  disable and 

S

OUT

 high Z 

t

DSZ

2 CL=100 

pF  — — 100 

Time lag between CS1 enable and 

TP

OUT

 output 

t

DPZ

1 CL=100 

pF  — — 100 

Time lag between CS1 disable and 

TP

OUT

 high Z 

t

DPZ

2 CL=100 

pF  — — 100 

ns 

 

Downloaded from 

Elcodis.com

 

electronic components distributor

 

Содержание RTC-4553AC

Страница 1: ...MQ342 01 Application Manual Real Time Clock Module RTC 4553AC Downloaded from Elcodis com electronic components distributor...

Страница 2: ...granted by implication or otherwise and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third par...

Страница 3: ...8 2 2 Control Registers 10 8 3 How to use 12 8 3 1 Data Read 12 8 3 2 Data Write Modify 12 8 3 3 Initialize 12 8 3 4 Timing Pulse Output 12 8 3 5 Sample Operation Flow Charts 13 8 3 6 CS1 and CS0 Ope...

Страница 4: ...s a very compact real time clock module with permanent calendar and serial data input output The module is designed for E mater time accuracy is within 5 10 6 0 432 sec day It incorporates a heat resi...

Страница 5: ...For normal operation and bus access supply 5 V 10 or 3 V 10 For backup battery operation provide a voltage of 2 V or higher See Note 1 CS0 Chip select 0 11 I This pin serves to select the RTC While C...

Страница 6: ...emperature TOPR No condensation 30 70 C 6 Frequency characteristics GND 0 V Item Symbol Condition Rating Unit 5 10 6 Frequency precision f fo Ta 25 C VDD 5 0 V AC 0 432 sec day Frequency temperature c...

Страница 7: ...N 0 V 2 0 2 0 A Oscillation startup time Ts Ta 25 C 3 0 s 2 AC Characteristics GND 0 V Ta 30 C 70 C VDD 5 V 10 Item Symbol Condition Min Typ Max Unit SCK frequency fCLK 500 kHz SCK L time tWCKL 1 0 SC...

Страница 8: ...startup time TS Ta 25 C 3 0 s 2 AC Characteristics GND 0 V Ta 30 C 70 C VDD 3 V 10 Item Symbol Condition Min Typ Max Unit SCK frequency fCLK 300 kHz SCK L time tWCKL 1 5 SCK H time tWCKH 1 5 SCK paus...

Страница 9: ...tps tDSO 90 1 8 1 10 10 90 10 tDPZ2 tDPZ1 90 90 10 90 90 90 90 10 10 10 10 tSWR tHWR tDSZ2 tHCS tWCKH tWCKL tSCS 1 f CLK tHD tSD tDSZ1 CS0 SCK SIN WR SOUT CS0 SCK SCK SOUT CS1 TPOUT Downloaded from E...

Страница 10: ...A1 A0 D3 D2 D1 D0 0 0 0 0 0 RA3 RA2 RA1 RA0 RA4 RA8 RA12 RA16 RA20 RA24 RA28 RA32 RA36 RA40 RA44 RA48 RA52 RA56 MS0 MODE 0 Address Counter control register A3 A2 A1 A0 Register designation D3 D2 D1 D0...

Страница 11: ...de Meaning 0 No carry Time calendar counter read write possible 1 Carry Time calendar counter read write prohibited PONC Power on clear detection At power on the power on clear function automatically...

Страница 12: ...24 hour format is switched during clock operation 4 Day of the week digit counter A3 A2 A1 A0 Name D3 D2 D1 D0 Register contents 0 1 1 0 W 0 w4 w2 w1 Day of the week digit counter Counts values from...

Страница 13: ...s written to the 30ADJ bit the bit automatically resets itself to 0 within 76 3 s The 30 second adjustment function also resets fractions below full seconds The TPOUT 1 10 Hz duty changes for one cycl...

Страница 14: ...bit is the power on clear detection bit see next page It is set to 1 when power on clear is detected The PONC bit is reset 1 0 by setting the SYSR bit to 1 c D1 bit bit marked When this bit is read da...

Страница 15: ...ounter can be incremented via the 1 hour digit counter 8 3 3 Initialize 1 System reset When the SYSR bit in the control register 3 is set to 1 all logic bits are initialized The SYSR bit is reset to 0...

Страница 16: ...e BUSY bit down transition was detected If the process takes longer the BUSY bit must be checked again for continued processing It is advisable to start the setting from the year digit to prevent sett...

Страница 17: ...00 to 2 00 the hour digit must be reset CNTR 1 For the year CNTR is used separately for the 1 year digit and 10 year digit Performing CNTR on the 1 year digit does not change the 10 year digit Conver...

Страница 18: ...rcuits To internal circuits To internal circuits From internal circuits From internal circuits CS1 CS0 WR SCK SIN SOUT TPOUT 8 3 7 System Power Down During Interface Operation When the system power go...

Страница 19: ...t may not be performed correctly Be sure to verify correct operation Note 2 Within the voltage range for data retention and clock operation 2 0 V 5 5 V power on reset is designed not to be performed u...

Страница 20: ...mented Carry from hour digit Feb 29 00 Feb 29 01 Mar 01 01 When the following non existent data are set February 30 incrementing the 10 day digit causes an overflow in the 10 day digit clearing the 1...

Страница 21: ...and data Data Address 10 second digit contents Data Address 1 second digit contents Data WR CSo SCK Don t care SIN Undefined SOUT When specifying the next data read access the previously accessed add...

Страница 22: ...ted by 1 For continuous write operations the CS0 must be kept L for the required number of increments 1 SIN Input at leading edge of SCK SOUT Output at trailing edge of SCK 4 SRAM data write example d...

Страница 23: ...rementing steps Data after incrementing 0 4 4 8 3 11 10 digit is carried automatically Control register and SRAM Address and 4 bit data are written The selected counter register or RAM address data ar...

Страница 24: ...7 4 0 2 14 8 7 1 1 4 1 4 5 4 1 27 1 27 6 7 62 0 7 Unit mm 9 2 Marking layout RTC 4553AC SOP 14pin Symbol mark Frequency tolerance indication Indication Frequency tolerance AC 5 10 6 Model identifier...

Страница 25: ...e fT Frequency deviation at given temperature fV Frequency deviation at given voltage 3 Calculating the daily deviation Daily deviation f f 86400 seconds For example at f f 11 574 10 6 the deviation i...

Страница 26: ...lfunctions due to noise Therefore pull up or pull down resistors should be provided for all unused input pins except L1 L5 pins 11 2 Notes on packaging 1 Soldering temperature conditions If the temper...

Страница 27: ...01 FRANCE FRENCH Branch Office 1 Avenue de l Atlantique LP 915 Les Conquerants Z A de Courtaboeuf 2 F 91976 Les Ulis Cedex France Phone 33 0 1 64862350 Fax 33 0 1 64862355 ASIA CHINA EPSON CHINA CO LT...

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