Sanyo PLV-WF20, Руководство по обслуживанию

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Electrical Adjustment
GROUP NO. ITEM FUNCTION RANGE INITIAL VALUE NOTE
2 R SIG Center 0 ~ 63 32
3 G Gain Control 0 ~ 255 194
4 B Gain Control 0 ~ 255 194
5 R Gain Control 0 ~ 255 194
6 G Bright Control 0 ~ 255 0
7 B Bright Control 0 ~ 255 0
8 R Bright Control 0 ~ 255 0
9 G VCOM Control 0 ~ 255 104 * Common Center Adj. (G)
10 B VCOM Control 0 ~ 255 104 * Common Center Adj. (B)
11 R VCOM Control 0 ~ 255 104 * Common Center Adj. (R)
12 G SID Control A 0 ~ 255 16
13 B SID Control A 0 ~ 255 16
14 R SID Control A 0 ~ 255 16
15 G SID Control B 0 ~ 255 166
16 B SID Control B 0 ~ 255 166
17 R SID Control B 0 ~ 255 166
18 G FRINV 0 ~ 1 0
19 B FRINV 0 ~ 1 0
20 R FRINV 0 ~ 1 0
290 Panel-LR * LCD Panel L/R Setting
0 Panel Type _LR Read only 0 : Type - L / 20 : Type - R 0 / 20 0
1 Panel Type L/R _Chenge Select Panel type L / R and Gamma Data Initialize 0 ~ 20 10
300 CXD3815 - On Board
0
1
2 CVBS Y Level
CVBS / Y Input Gain Adjustment (Composite /
S-VIDEO)
0 – 255 210 / 210 * AV Video SIgnal Adj.(Y)
3 CVBS C Level C Input Gain Adjustment (Composite / S-VIDEO) 0 – 255 140 / 140 * AV Video SIgnal Adj.(C)
4 Sub Hue Tint Adjustment CVBS / S Input 0 – 63 32
5 HS Slice Level H Sync Slice Level 0 – 15 4
6 HS Slice offset H Sync Slice Level Offset 0 – 15 5
7 VS Slice Level V Sync Slice Level 0 – 15 6
8 VS Slice Level AD Clock 0 – 15 6
9 Sampling Phase V Sync Slice Level Offset 0 – 63 0
10 Pre Shoot Level Sub Sharpness (Common value of CVBS/S-VIDEO) 0 – 15 8
11 Over Shoot Level Sub Sharpness (Common value of CVBS/S-VIDEO) 0 – 15 8
12 Y Filter Setting Y Filter (Common value of CVBS/S-VIDEO) 0 ~ 7 5
13 C Filter Setting C Filter (Common value of CVBS/S-VIDEO) 0 ~ 7 5
14 NTSC / PAL Detect
Setting NTSC / PAL Detect
1 : 96H / 1V
2 : 128H / 1V
3 : 160H / 1V - PAL Ditect (Low)
0 ~ 3 1
301 CXA2239 - Option
0 OUT_GainR 0 ~ 255 0
1 OUT_GainG 0 ~ 255 0
2 OUT_GainB 0 ~ 255 0
303 FINE FPGA - Color Manegement
0 Y Range 0 ~ 32 8
1 Hue Range 0 ~ 20 10
2 Gain Range 0 ~ 50 30
3 Gm_Min Slope 0 ~ 10 3
4 GM_Max Slope 10 ~ 30 18
5 GM_Converge 1 ~ 5 3
6 – – –
7 – – –
8 COLM_GET_KIND_Y_ud 1 ~ 9 9
9 – – –
10 – – –
11 Same Hue 1 ~ 10 3
12 Cut_UV Norm 0 ~ 64 5
13 Cur_Min Y 0 ~ 127 0
14 Cur_Max Y 128 ~ 255 255
15 CM_IsAccess 0 : Enable / 1 : Disable 0 ~ 1 1
16 FINE FPGA Thru Mode FPGA Through Mode 0 ~ 1 0
320 ILS51002 - Common
0 GREEN_OFFSET (r12-13) RGB_Analog / Component / CVBS(S) 0 ~ 1023 512/512/512
1 RED_OFFSET (r14-15) RGB_Analog / Component / CVBS(S) 0 ~ 1023 512/512/512
2 BLUE_OFFSET (r16-17) RGB_Analog / Component / CVBS(S) 0 ~ 1023 512/512/512
3 GREEN_GAIN (r18-19) RGB_Analog / Component / CVBS(S) 0 ~ 1023 188/188/188
4 RED_GAIN (r1A-1B) RGB_Analog / Component / CVBS(S) 0 ~ 1023 188/188/188
5 BLUE_GAIN (r1C-1D) RGB_Analog / Component / CVBS(S) 0 ~ 1023 188/188/188
6 PLL_Pre-coast (r21) 0 ~ 255 8
7 PLL_Post-coast (r22) 0 ~ 255 13
8 ABLC Configuration - ABLC disable (r27) 0 ~ 1 0
9 ABLC Configuration - Offset DAC
Range
(r27) 0 ~ 1 1
10 ABLC Configuration - ABLC pixel width (r27) 0 ~ 3 1