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IC BLOCK DIAGRAM & DESCRIPTION
IC800 ZR36748(DVD Player AV Decorder)
Pin No.
Boot selection, debug interface, GPIO pin, test mode (23pin)
40
208
2
41
42
43
44
45~47
49
51
8
7
5,6
4
197
196
195
177
3
206
PLL signal (4 pin)
157
161
160
194
Analog video port (5pin)
169
I/O
I#
I/O#
I
O
I
I/O
I/O#
I
I/O
I/O
I/O
I
I/O
O
I/O#
I
I/O#
O
I/O
I/O
I/O#
O
I/O#
O
I/O#
O
I/O#
O
I/O#
I
ID
ID
ID
AO
ID#
I/O
AO
Name
BOOTSEL1
GPCI/O[0]#
NMI
DUPTD
DUPRD
GPCI/O[1]
GPCI/O[2]#
SSCSRQ
GPCI/O[3]
GPCI/O[4]
GPCI/O[5-7]
GPCI/O[8]#
SSCRXD
GPCI/O[9]#
SSCTXD
GPCI/O[10]#
SSCCLK
GPCI/O[11]#
SSCRRQ
GPCI/O[12-13]
GPCI/O[14]
GPCI/O[15]#
HSYNC
GPCI/O[16]#
VSYNC
GPCI/O[17]#
VCLK x 2
GPCI/O[18]#
COSYNC
GPCI/O[19]#
BOOTSEL2
TESTMODE
RESET#
GCLK
XO
PLLCFGP#
GPCI/O[20]
CVBS/G/Y
(DAC A)
Function
CPU software starting basis select I. Low:starting by flash memory.
High : starting by down loaded program from UART.
Controled general I/O by microcomputer software.
MN1 interrupt I.
Debug UART data O.
Debug UART (or IrDA) data I.
Controled general I/O by microcomputer software.
USE general interrupt I.
Controled general I/O by microcomputer software.
Use general interrupt I.
SSC mode : synchronization communication requeat reception.
Controled general I/O by microcomputer software.
Use general interrupt I.
N/C
Controled general I/O by microcomputer software.
Use general interrupt I.
Controled general I/O by microcomputer software.
Use general interrupt I.
SSC mode : synchronization communication data reception.
Controled general I/O by microcomputer software.
SSC mode : synchronization communication data transmission.
Controled general I/O by microcomputer software.
SSC made : synchronization communication clock reception.
Controled general I/O by microcomputer software.
SSC mode : synchronization communication acknowledge transmission.
Controled general I/O by microcomputer software.
Controled general I/O by microcomputer software.
Controled general I/O by microcomputer software.
Horizontal synchronization O.
Controled general I/O by microcomputer software.
Vertical synchronization O.
Controled general I/O by microcomputer software.
VCLK x 2 O.
Controled general I/O by microcomputer software.
Cosync O.
Controled general I/O by microcomputer software.
Readed by BOOT ROM after hardware reset and used when select flash
ROM or flash ROM + SRAM set.
Direct connect to GNDP when usually operation.
Reset I (Active low).
Initialize process start RESET# signal deassert.
27.000MHz clock for main process generation or xtal I.
Connected xyal to GCLK O.
N/C when not use xtal.
Process clock PLL set I.
Can change when RESET# assert.
Usually operation : low, RESET assert term.
Controled general I/O by microcomputer software.
YC O : CVBS signal O.
RGB O : G signal O.
YUV O : Y signsl O.