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COMe-mEL10 - User Guide Rev. 1.1
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Sub-screen
Next Level Sub-screens / Description
System Agent
(SA)
Configuration>
(continued)
CRID Support>
SA CRID and TCSS CRID control for Intel SIPP
[Enabled, Disabled]
Above 4 GB
MMIO BIOS
Assignment>
Enables automatically when aperture size is set to 2048 MB.
[Enabled, Disabled]
Sub-screen
Next level Sub-Screens / Description
PCH-IO
Configuration>
PCI Express
Configuration>
DMI Link ASPM
Control>
Control of Active State power management of the DMI
[Disable, L0s, L1, L0sL1, Auto]
Peer Memory
Write Enable>
[Enabled, Disabled]
Compliance
Test Mode>
[Enabled, Disabled]
PCH PCI
Express Clock
Gating>
PCH PCI express clock gating (power management) for each
root port.
[Platform-POR, Enabled, Disabled]
PCIe Function
Swap>
Disabled prevents PCIe root port function swap. If any
function other than 0
th
is enabled, 0
th
will become visible.
[Enabled, Disabled]
PCIe EQ
Settings>
PCIe EQ
Override>
Choose PCIe EQ setting. Only use when
you have a thorough understanding of
the equalization process.
[Enabled, Disabled]
PCIE Express
Root Port
[1 to 4]>
PCIe Express
Root Port [#]>
Control the PCIe Express Root Port
[Enabled, Disabled]
Connection
Type>
Built-in: A built-in device is connected to
this root port. Slot implemented bit will
be clear.
Slot: This root port connects to a user
accessible slot. Slot implemented boot
will be set.
[Built-in, Slot]
ASPM>
Sets ASPM level:
Force LO: Forces all links to L0 state
Auto : BIOS auto configure
Disable: Disables ASPM
[Disable, L0s, L1, LOsL1, Auto]
L1 Sub-states>
PCIe L1 sub-state settings:
[Disabled, l1.1, l1.1 &L1.2]
ACS>
Access Control Service
[Enabled, Disabled]
PTM>
Precision Time Measurement
Enabled, Disabled]
DPC>
Downstream Port Containment
[Enabled, Disabled]