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SGH-E700 Circuit Description
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4
The hardware sequencer built in this device allows playing of the complex music without giving excessive load to the
CPU of the portable telephones. Moreover, the registers of the FM synthesizer can be operated directly for real time
sound generation, allowing, for example, utilization of various sound effects when using the game software installed in the
portable telephone.
YMU762 includes a speaker amplifier with high ripple removal rate whose maximum output is 550mW (SPVDD=3.6V).
The device is also equipped with conventional function including a vibartor and a circuit for controlling LEDs
synchornous with music.
For the headphone, it is provided with a stereophonic output terminal.
For the purpose of enabling YMU762MA3 to demonstarte its full capablities, Yamaha purpose to use "SMAF:Synthetic
music Mobile Application Format" as a data distribution format that is compatible wiht multimedia. Since the SMAF takes
a structure that sets importance on the synchronization between sound and images, various contents can be written into it
including incoming call melody with words that can be used for traning karaoke, and commercial channel that combines
texts, images and sounds, and others. The hardware sequencer of YMU762MA3 directly interprets and plays blocks
relevant to systhesis (playing music and reproducing ADPCM with FM synthesizer) that are included in data distributed in
SMAF.
5. Memory
signals in the OM6357 enable two memories. They use only one volt supply voltage, VDD3 in the PCF50601. This
system uses Samsung's memory, KBB06A300M-T402. It is consisted of 128M bits flash NOR memory and 128M bits
flash NAND memory and 32M bits UtRAM. It has 16 bit data line, HD[0~15] which is connected to OM6357 and
MV317S. It has 23 bit address lines, HA[1~23]. CS_NAND and NCSRAM signals is chip select.
Wrting process,
HWR_N is low and it enables writing process to flash memory and SRAM. During reading process, HRD_N is low and
it enables reading process to flash memory and SRAM. Each chip select signals in the OM6357 select memory among 2
flash memory and UtRAM. Reading or writing procedure is processed after HWR_N or HRD_N is enabled. Memories use
reset, which is VDD3 delay from PCF50601. HA[22] signal enables lower byte of SRAM and HA[22] signal enables
higher byte of SRAM.
6. OM6357
OM6357 is consisted of ARM core and DSP core. It has
8x1Kword on-chip program/data RAM, 55 Kwords
on-chip program ROM
in the DSP. It has 4K*32bits ROM and 2K*32bits RAM in the ARM core. DSP is consisted
of KBS, JTAG, EMI and UART. ARM core is consisted of EMI, PIC(Programmable Interrupt Controller),
reset/power/clock unit, DMA controller, TIC(Test Interface Controller), eripheral bridge, PPI, SSI(Synchronous Serial
Interface), ACC(Asynchronous communications controllers), timer, ADC, RTC(Real-Time Clock) and keyboard interface.
KBIO(0:7), address lines of DSP core and HD[0~15]. HA[1~23], address lines of ARM core and HD[0~15], data lines of
ARM core are connected to memory, YMU759. MV317S(Camera DSP Chip) controls the communication between ARM
core and DSP core.
CS_NAND, NCSRAM, NCSFLASH in the ARM core are connected to each memory. HWR_N and HRD_N control the
process of memory. External IRQ(Interrupt ReQuest) signals from each units, such as, PMU need the compatible process.
KBIO[0~7] receive the status from key and RXD0/TXD0/irDA_DOWN are used for the communicatios using IRDA and
data link cable(DEBUG_DTR/RTS/TXD/RXD/CTS/DSR).
It has JTAG control pins(TDI/TDO/TCK) for ARM core and DSP core. It recieves 13MHz clock in CKI pin from
external TCXO. ADC(Analog to Digital Convertor) part receives the status of temperature, battery type and battery voltage.
