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SGH-A500 Flow Chart of Troubleshooting and Circuit Diagrams
6-
14
16. Baseband Processor Circuit Diagram
4
Time Changed
C
QA CH
K
MFG ENGR CH
K
Drawn by
Address
5
D
Drawing Numbe
r
D
3
Shee
t
VMI
C
E
LAUTERBACH
COMPANY NAME
7
CLOSE TO PIN1
1.9B
REV
5
4
8
6
2
of
1
8
TITLE
:
Engineer
F
4
A
C
E
F
City
3
2
1
B
HEAD SET FPCB
Size
EMULATOR
A
B
Date Changed
R&D CH
K
DOC CTRL CH
K
(HP_PWR
)
6
SGH-A500_REV1.9
B
A3
user10
2002 - 09 - 30
1:51:19 pm
KIM H.
K
KIM. H.
K
6
Changed by
7
C7
WRQ
100NF
C404
VSS2.2
VSS2.3
P5
P1
3 VSS2.4
N1
5
VSSA|RTC
VSSD
H1
K2
VSSR
K5
VSST
G 2
VSSV
VSSV2
1 D3
VSSV2
2
E3
VSSX
G 1
H4
VMI
C E1
VREF
G5
B2 VSS1.0
VSS1.1
B1
4
G 1
4 VSS1.2
VSS1.3
P2
B5 VSS2.0
A
VSS2.0
B
B1
1
E1
4 VSS2.0
C
VSS2.1
P9
J14
VDD2.4
R1
3
VDDA
M1
3
VDDD
H3
VDDR
K3
N1
3 VDDRTC
K1
VDDT
G 3 VDDV
VDDV21
C2
E4
VDDV22
VDDV23
E5
VDDX
P7
B1 VDD1.0
B1
5 VDD1.1
VDD1.2
G 1
5
R2 VDD1.3
VDD2.0A
A5
A1
1 VDD2.0B
VDD2.0C
E1
5
R9 VDD2.1
VDD2.2
J15
R5 VDD2.3
T_OUT11|CC19IO
H1
4
T_OUT12
T_OUT
2
L13
K1
3 T_OUT
3
T_OUT
4
J13
H1
3 T_OUT
5
T_OUT
6
K1
2
J12 T_OUT7|PD.
6
T_OUT
8
H1
2
L11 T_OUT9|PD.
8
VBAT
N1
VCXO2_E
N
TRIG_IN
N4
N3
TRIG_OUT
N6
TRST#
M4 TVCO
R12
TXD
0
TXD
1
N1
2
TXD
D
C5
T_OUT
0
L15
L14 T_OUT
1
G 1
1 T_OUT10|DSPIN1
F11
M1
2
RXD
D
D5
C6
SCLK
SSCCLK
P1
1
L 3 TBAT
N5
TCK
TD
I
P4
TD
O
R4
TENV
L 4
TFSD
D4
P6
TM
S
C4
RFSD
H1
5 RFSTR0
RFSTR1
M1
5
K11
RFSTR2
RFSTR3
J1
1
L12
RFSTR4|EX2IN
RSTOUTQ|F.2
A2
P1
4
RTCOUT
P1
5
RTCOUT|F32K
X
P12
RXD
0
RXD
1
QGUARD
P1
QR
M2
M1
QR
X
QT
J3
J4
QT
X
RDQ D7
M7
READYQ|PC.
1
P3
RESET_IN_Q
RFCL
K
K1
4
K1
5 RFDATA
M3 RFREF
E8
H1
1
NC
3
NC
4
A15
R15
NC
5
L8
NC
6
R1
NC
7
NC
8
H5
J5
NC
9
C3
NGUAR
D
PAOUT
H2
B3
PDOUT|A23
KP
8
KP
9
R1
1
MICN1
F 1
MICN2
F 3
F 2
MICP
1
F 4
MICP
2
MON1
M5
L5
MON2
MRST R1
4
N1 1
MTSR
A1
NC
1
NC
2
J1
IT
J2
IT
X
R7
KP
0
KP
1 R8
P8
KP
2
KP
3 N8
M8
KP
4
KP
5
N9
R1
0
KP
6
KP
7
P1
0
N1 0
DSPOUT1|A22
EPN1 C1
EPN2
E2
D2
EPP
1
D1
EPP
2
M1 4
F13M
F32
K N1 4
HLDAQ|DSPIN0
M6
L1
IR
IREF
F5
L2
IR
X
D1
5
D8
E1
3
D2
D3
E1
2
D1
3
D4
D5
D1
2
C13
D6
D7
C12
C11
D8
D9
D1
1
A3
DSPOUT
0
E11
D6
CS1Q
CS2Q
E6
CS3Q
G1
2
G1
3
CS4Q
F13
D0
D1
F12
C10
D1
0
D1
1
D1
0
C9
D1
2
D1
3
D9
C8
D1
4
CC02IO|RF.0
E10
CC06I
O
CCI
N
L 6
M1 0
CCI
O
L 9
CCIOSW
M9
CCLK
CCRS
T
L 7
CCVZQ
L10
CLKOUT|PC.
0
R6
CLKXM|A21
B4
CS0Q
A1 4
A13
B13
A7
A8
A12
B12
A9
AF
C
R3
G4
AGND
BHEQ
E7
BREF
K4
N2 BTEC
CC00IO|PC.
2
N7
CC01IO|PE.
2
M1
1
E9
B8
A15
A16
A7
B7
A17
A18
A6
B6
A19
A2
D1
5
A20
A4
D1
4
A3
A4
C15
C14
A5
A6
A0
F15
F14
A1
A10
A10
B10
A11
A12
A9
B9
A13
A14
A8
U401
DATA_DET1
C44
6
NC
RESET
C450
27P
F
VANA
VBA
T
R408
30 K
100N F
C41
8
VANA
6.3V
10U F
C409
TX
TP434
TP435
R410
10K
100N F
C477
AGND
6
7
7
8
8
9
9
12
13
13
14 14
15 15
2
2
3
3
4
4
5
5
6
CN402
1
1
10 10
11
11
12
AGND
C449
100N F
AGND
VBAT
TP3
TP433
VANA
TP432
27PF
R430
NC
VIN
T
C448
2.2
K
100N F
R41
2
TP40
7
C40
8
AUTO_PWR 1
R405
0
TP1
TP2
18PF
AGND
VDD_SD
C423
AGN
D
100N F
C447
C478
100N F
10NF
TCK1
C411
4
5
5
66
7
GG
89
GG
10
CN40
1
1 1
2
2
3 3
4
560PF
AGND
C445
6.3V
C407
2.2U
F
22 K
100NF
C41
6
C430
22UF
6.3V
R418
F_WE
AGN
D
VANA
27PF
C443
18PF
C428
R415
2.4
TMS1
27PF
C444
AGND
VSI M
TDO1
TP4
C41
2
10N
F
6.3
V
10U F
C432
1.5K
R428
VINT
AGND
C439
27PF
VRTC
R402
150K
C414
100N
F
A_ P
C431
22U F
6.3
V
VRF2
RX
VINT
C436
47PF
R409
330K
VINT
RXDD
TP428
33 K
R453
1M
R452
TDI1
VINT
SCLK
TP429
TRST1
TFSD
5.1
R404
100K
AGND
TP431
R416
RFSD
TP430
2.2 K
R42 7
AGND
TXDD
AGND
NC
R417
C479
27PF
2
3
4
1
OSC40
1
V4
5.1
R403
33K
R450
GND
39PF
C401
100NF
C417
0
R414
100K
AGND
VSI M
R411
C480
100N F
AGND
C41
3
100N
F
C41
0
100NF
U410-1
4
3
2
8
1
220K
1.5K
R413
TCK
TD
I
TD
O
TM
S
TRIG_IN
TRIG_OUT
TRST
TXD
0
TXD
1
LED_CT
L
F-RY_BY
VCXO_E
N
WRQ
DATA_DET
R42 9
KP4
KP5
KP6
KP7
KP8
KP9
MON1
MON2
DISP_SID
GR_LED
AB
AX
RDQ
RESETQ
FLASH_W
R
POLY_RST
EP_INT
DATA_DE
T
RTCOUT
RXD
0
RXD
1
DISP_SCL
K
D(3)
D(4)
D(5)
D(6)
D(7)
D(8)
D(9)
RD_LED
EPN2
EPP2
FSYS_B
B
B
BX
KP0
KP1
KP2
KP3
BHEQ
FLIP_SN
S
MOTOR_EN
HS_DE
T
A(21)
CCI
O
CTS
CCL
K
CCRS
T
AUTO_PWR
SEND_EN
D
FLASH_SE
L
SRAM_SEL
POLY_IRQ
POLY_EN
D(0)
D(1)
D(10)
D(11)
D(12)
D(13)
D(14)
D(15)
D(2)
HS_DET
SEND_EN
D
A(0)
A(1)
A(10)
A(11)
A(12)
A(13)
A(14)
A(15)
A(16)
A(17)
A(18)
A(19)
A(2)
A(20)
A(3)
A(4)
A(5)
A(6)
A(7)
A(8)
A(9)
A(22)
TM
S
T D
O
RESETQ
TRST
MON2
TXD1
RXD1
TRIG_OUT
EPP2
MICP
2
T C
K
T D
I
RTS
MICP2
AUTO_PWR
VINT
RESET
Q
BP_VF
CCIO
EPN
1
EPP
1
POLY_CLK
EP_SC
L
CCL
K
CCRS
T
PLLO
N
ISENSE
DISP_C
S
EP_SD
A
DISP_R
S
DISP_RS
T
A(1:20)
BL_LED
MICP
1
TEMP
MON1
TRIG_IN
TX_POWE
R
RF_DAT
A
RF_CLK
RF_E
N
AF
C
TX1800_RX900
TX900_RX1800
TXONPA
D(0:15)
TDI
T D
O
TM
S
T C
K
TRST
VBAT
TXD0
RXD0
WRQ
T A
+