RTD Embedded Technologies, Inc.
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23
SYNC25104HR/
SYNC35104HR
User’s Manual
NOTE: If the number of messages sent by the GPS receiver in every second
is increased, it is recommended to use a higher baud rate because the
low speed connection can easily be filled up with messages.
GPS Antenna
Most GPS antennas are “active” which means they have a low noise amplifier (LNA) built into the antenna that requires a power source for the
GPS module. While the SYNC35104HR/25104HR will work with a passive antenna, better performance will be achieved with an active
antenna. The SYNC35104HR/25104HR pr3.3V/ for active GPS antennas.
COCOM Limits
The GPS module disable tracking when both altitude (18,000m) and speed (515 m/s) limits are exceeded. However, the module has an
acquisition altitude limit of 10,000m. So, it cannot be powered on and acquire a position above 10,000m, but it will continue tracking if a position
is acquired below 10,000m and then the module goes higher.
LEA-M8F GNSS Receiver Documentation
The up to date documentation of the GNSS receiver can be found on the manufacturer’s website. See the links below:
Datasheet:
https://www.u-blox.com/en/docs/UBX-14001772
Receiver description:
https://www.u-blox.com/en/docs/UBX-13003221
5.2.2
SI5395
F
REQUENCY
S
YNTHESIZER
The SYNC35104HR/25104HR combines the GPS disciplined oscillator with an ultra-low jitter, multiple output frequency synthesizer. The
generated output frequencies can range from 100Hz-1028MHz and the RMS phase jitter can go as low as 69fs. The synthesizer chip can be
programmed by the Clock Builder Pro software, the configuration can be stored in the on-chip non-volatile memory. For detailed descriptions
and further information please refer the following manuals:
Datasheet:
https://www.silabs.com/documents/public/data-sheets/si5395-94-92-a-datasheet.pdf
Reference Manual:
https://www.silabs.com/documents/public/reference-manuals/si5395-94-92-family.pdf
SI5395 Block Diagram
The block diagram of SI5395 can be seen on Figure 9. The 4 inputs of the chip are connected as follows:
-
IN0: 10MHz onboard OCXO
-
IN1: 30.72MHz GPS clock
-
IN2: not connected
-
IN3/FB_IN: connected to OUT9A (to enable Zero Delay Mode operation)
The DSPLL block has an on-board 48MHz crystal oscillator.
The outputs are connected according to Table 11:
Table 11: SI5395 outputs
Output Destination
Output standard
OUT0A not connected
OUT0 SyncBus lane 2
LVCMOS 3.3V
OUT1 SyncBus lane 1
LVCMOS 3.3V
OUT2 CN6 pin 13 (+), 14 (-)
any differential
OUT3 CN6 pin 9 (+), 10 (-)
any differential
OUT4 CN6 pin 5 (+), 6 (-)
any differential
OUT5 CN6 pin 1 (+), 2 (-)
any differential
OUT6 CN10
LVCMOS 3.3V