RTD Embedded Technologies, Inc.
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25
DMx820 User’s Manual
Internal Architecture
A diagram of the standard I/O is shown in Figure 11. Each digital I/O pin can be an input, output, or peripheral output. The peripheral outputs
are the Pulse Width Modulators, FIFO, Timer/Counters, etc.
D
Q
PORTx_MODE
D
Q
PORTx_OUTPUT
0
D
Q
PORTx_PERIPH_SEL
1
Peripheral 3
D
Q
PORTx_TRISTATE
D
Q
Peripheral Input
D
Q
PORTx_INPUT
Peripheral 2
Peripheral 1
Peripheral 0
Data Readback
Figure 9: Digital I/O Block Diagram
FIFOs
The DMx820HR provides two FIFOs to buffer data going into and out of the board. Each FIFO is 16-bit wide and 2,097,661 Words deep. The
input strobe, output strobe, and data input for each FIFO can be individually selected. The output data is made available to the peripheral
outputs, and also the PCI interface.
Each FIFO is attached to a DMA Channel in the PLX chip. FIFO0 is attached to DMA0, and FIFO1 is attached to DMA1.
FIFO0 can have its input data attached to its output data. In this case, the same data is repeated forever. This is useful for some types of
pattern generation.
Internally, the FIFO system consists of a single 8MB SDRAM device, with 255-word input and output buffers for each channel. When data is
available in the input buffer, it is moved into the area of SDRAM device for that channel. When data is in the SDRAM device, and there is room
available in the output buffer, data is moved to the output buffer. All of the internal data movement is handled automatically. Greatest data
efficiency is achieved when there are at least 128 words of data in the FIFO.
The FIFO also provides “Write Request” and “Read Request” signals. For these signals, the internal buffers are monitored to
signal when data
can be sent into, and read from the FIFO. The “Write Request” is asserted when there
are at least 256 words of space available in the FIFO,
and negated when there are
less than 128 words available. The “Read Request” is asserted when at least 256 words of data is in the FIFO,
and negated when there is less than 128 words of data. Using these signals guarantees a burst of at least 128 words, which provides for
efficient communication over the PCI bus, and robustly guards against over-run and under-run conditions. However, it does not allow for the
FIFO to be completely filled or emptied.
There is a total of 45 M-words per second of available bandwidth for the entire FIFO system. This bandwidth is allocated between all input and
output sources. This is assuming that at least 256 Words stay in the FIFO at all times to maximize bursting (i.e., the Read Request and Write
Request are used for DREQ). If only one word is available in the FIFO (i.e. Not Empty is used as for DREQ) the available bandwidth drops to
3.75 M-words per second. When a FIFO is looped, the data must be read and written. The table below shows examples of configurations and
their maximum data rate. Note that for uniform sampling (samples are taken at uniform sampling intervals) the data rate must be an integer
divisor of the 25 MHz overall clock.
