rtd DM35425, Руководство пользователя

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RTD Embedded Technologies, Inc.
| www.rtd.com 51 DM35425HR User’s Manual
6.6 BAR2 – External Clocking Functional Block
This function block provides an interface to the External Clocking. It is used to input or output the source of the CLK_BUSn.
Table 22:External Clocking Functional Block
Offset 0x03 0x02 0x01 0x00
H
eader
FB + 0x00
FB_ID
FB + 0x04 FB_DMA_BUFFERS FB_DMA_CHANNELS Reserved Reserved
FB + 0x08 EXT_CLK_EDGE EXT_CLK_DIR EXT_CLK_GATE_IN EXT_CLK_IN
FB + 0x0C EXT_CLK_PW5 EXT_CLK_PW4 EXT_CLK_PW3 EXT_CLK_PW2
FB + 0x10 EXT_CLK3_CFG EXT_CLK2_CFG EXT_CLK_PW7 EXT_CLK_PW6
FB + 0x14 EXT_CLK7_CFG EXT_CLK6_CFG EXT_CLK5_CFG EXT_CLK4_CFG
6.6.1 FB_ID (R
EAD
-O
NLY
)
This is the functional block ID. This register should read 0x00000002 for the External Clocking functional block.
6.6.2 FB_DMA_CHANNELS (R
EAD
-O
NLY
)
Has no DMA channels, reads 0
6.6.3 FB_DMA_BUFFERS (R
EAD
-O
NLY
)
Has no DMA buffers, reads 0
6.6.4 EXT_CLK_IN (R
EAD
-O
NLY
)
This register provides the current value on the External Clocking lines. The bits in the register correspond with the External Clocking pins as
follows:
Bit CN3
Pin
Number
CLK_BUSn Signal
5 45 7 EXT_CLK_7
4 44 6 EXT_CLK_6
3 43 5 EXT_CLK_5
2 42 4 EXT_CLK_4
1 41 3 EXT_CLK_3
0 39 2 EXT_CLK_2
6.6.5 EXT_CLK_GATE_IN (R
EAD
O
NLY
)
This register provides the current value on the External Clocking Gates lines. External Clocking Gates can only be used when inputting an
external clock. The bits in the register correspond with the External Clocking Gates pins as follows:
Bit CN4
Pin
Number
CLK_BUSn Signal
5 45 7 EXT_CLK_GATE7
4 44 6 EXT_CLK_GATE6
3 43 5 EXT_CLK_GATE5
2 42 4 EXT_CLK_GATE4
1 41 3 EXT_CLK_GATE3
0 39 2 EXT_CLK_GATE2
6.6.6 EXT_CLK_DIR (R
EAD
/W
RITE
)
Selects the direction of the External Clocking bits. 0=input, 1=output.
All pins default to inputs at power-up.