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DM35425HR User’s Manual
6
Register Address Space
The DM35425 FPGA code was built as a modular design, which allows each board function to have its own Functional Block (FB). Each
functional block was designed to work independent of each other. For this reason, we provide individual DMA channels, interrupts, clocks, and
FIFOs to each functional block.
The registers are described by their PCIe Base Address Register (BAR), which is defined in the PCI configuration space for this board. The
configuration space is generally handled by the operating system. For more information on how to use the configuration space, consult the
PCI
Local Bus Specification, Revision 3.0
from the PCI-SIG.
Register Types
There are several different types of registers that are referred to in this section. A description of each type is below.
Read/Write Registers: The value that is written to this register can also be read back.
Maskable Registers: This is a 32 bit register that consists of 16-bit data field in the upper word and a 16-bit mask value in the lower
word. For each bit in the data field, it is only written to the register if the corresponding bit in the mask field is
‘1’.
Sticky Registers: This is a status read register. When bit in
this register has a value of ‘1’, a ‘1’ needs written to
that bit to reset the
register to ‘0’.
This is typically used for interrupt status registers.
Read Only: This register can only be read.
NOTE: Writing to Read-Only registers may have unexpected results.
Clock Source
Clock sources can serve as either sample clocks for function blocks, or triggers for starting and stopping them. Function blocks can drive a
CLK_BUSn with a CLK_BUS_SRC (see the register descriptions for details on the possible values for CLK_BUS), and other function blocks
then trigger from that clock. This is what lets multiple function blocks start at the same time, or stop on the same trigger.
For example, to have all function blocks start the same time as ADC, you would set ADC to drive CLK_BUS2 with its start trigger. You would
then set all other function blocks to use CLK_BUS2 as their start trigger, and then start them. They will wait for the start trigger on CLK_BUS2
before they actually start. Start ADC, and all of the function blocks will start with it.
Below is the list of clock sources and the register value needed to select the source:
0x00:
System clock/immediate
0x01:
Never
0x02:
CLK_BUS2
0x03:
CLK_BUS3
0x04:
CLK_BUS4
0x05:
CLK_BUS5
0x06:
CLK_BUS6
0x07:
CLK_BUS7
0x08:
Channel Threshold
–
One of the channels has exceeded the High or Low threshold.
0x09:
Channel Threshold Inverted
–
All of the channels are within the High and Low threshold.
0x0A:
CLK_BUS2 Inverted
0x0B:
CLK_BUS3 Inverted
0x0C:
CLK_BUS4 Inverted
0x0D:
CLK_BUS5 Inverted
0x0E:
CLK_BUS6 Inverted
0x0F:
CLK_BUS7 Inverted
