rtd DM34216HR, Руководство пользователя

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49 DM34216HR
User’s Manual
BDM-610010056 Rev A
6.5.22 CH0_DATA (DIG_IN) (R
EAD
O
NLY
)
This register provides the current value on the Digital In lines. The bits in the register correspond with the Digital In pins as follows:
Bit CN3 Signal Name
31 34 DIO0.31
30 33 DIO0.30
29 32 DIO0.29
28 31 DIO0.28
27 30 DIO0.27
26 29 DIO0.26
25 28 DIO0.25
24 27 DIO0.24
23 26 DIO0.23
22 25 DIO0.22
21 24 DIO0.21
20 23 DIO0.20
19 22 DIO0.19
18 21 DIO0.18
17 20 DIO0.17
16 19 DIO0.16
Bit CN3 Signal Name
15 16 DIO0.15
14 15 DIO0.14
13 14 DIO0.13
12 13 DIO0.12
11 12 DIO0.11
10 11 DIO0.10
9 10 DIO0.9
8 9 DIO0.8
7 8 DIO0.7
6 7 DIO0.6
5 6 DIO0.5
4 5 DIO0.4
3 4 DIO0.3
2 3 DIO0.2
1 2 DIO0.1
0 1 DIO0.0
This is the same value that is written into the DMA INPUT FIFO.
6.5.23 CH1_DATA (DIG_OUT) (R
EAD
/W
RITE
)
The last value sent to the Digital Output. For each bit, a ‘0’ causes the output to be low, and a value ‘1’ causes the output to be high. Bit
assignments are the same as DIG_IN.
This register defaults to all 0 at power on.
If the current Mode is “Reset” or the associated DMA engine is set to “Clear”, a write to this register will immediately upda te the Digital I/O
Output. Bit assignments are the same as above.
6.5.24 CH2_DATA (DIG_DIR) (R
EAD
/W
RITE
)
The last value sent to the Digital I/O Direction.
If the current Mode is “Reset” or the associated DMA engine is set to “Clear”, a write to this register will immediately upda te the Digital I/O
Direction. Bit assignments are the same as above.
Selects the direction of the I/O bit. 0=input, 1=output.
All pins default to inputs at power-up.
6.5.25 CH
N
_FIFO_ACCESS (R
EAD
/W
RITE
)
This register provides direct access to the DMA FIFO. It can be used to access the data without the use of the DMA engine. The DMA engine
for this channel must be set to “Pause.” Each register access advances to the next sample.