rtd DM34216HR, Руководство пользователя

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43 DM34216HR
User’s Manual
BDM-610010056 Rev A
6.4.21 THRESH_LOW (R
EAD
/W
RITE
)
Signed 32-bit value indicating the low threshold. If the input signal drops below this value, an interrupt or clock can be generated until the
signal goes above this value. The 3 least significant bits are ignored from the actual threshold value.
NOTE: The threshold value should not exceed the ADC range. If the
threshold value exceeds the ADC range unexpected results will occur.
6.4.22 THRESH_HIGH (R
EAD
/W
RITE
)
Signed 32-bit value indicating the high threshold. If the input signal goes above this value, an interrupt or clock can be generated until the
signal goes below this value. The 3 least significant bits are ignored from the actual threshold value.
NOTE: The threshold value should not exceed the ADC range. If the
threshold value exceeds the ADC range unexpected results will occur.
6.4.23 LAST_SAMPLE (R
EAD
-O
NLY
)
The last sample read from the ADC Converter, after filtering. This is the same value that is written to the DMA FIFO.
•
When PACKED_DATA = 0, one sample stored in this register
•
When PACKED_DATA = 1, two samples stored in this register
o
B[15:0]: First Sample
o
B[31:16]: Second Sample
6.4.24 CH_FIFO_ACCESS (R
EAD
/W
RITE
)
This register provides direct access to the DMA FIFO. It can be used to access the data without the use of the DMA engine. The DMA engine
for this
channel must be set to “Pause.” Each register access advances to the next sample.