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BDM-610000088 Rev A Chapter 4: Using the cpuModule 69
Reset and Event Status Register
The cpuModule has several different signals on board which can cause a system reset. If a reset occurs, the
reset status register can be used to see which reset (or resets) have been asserted on the cpuModule. These
resets may be cleared by the user.
Similar to resets, there are several signals on the cpuModule which indicate that a special event has occured.
These may also be monitored and cleared by the user.
•
Examine Resets and Events : Reading from I/O ports 0xED0h through 0xED3 will indicate if a
reset has been asserted or if an event has occured. If a 1 is read, the corresponding reset has been
asserted. If a 0 is read from the bit, the reset has not been asserted. For events
•
Clear Reset and Event : Each reset and event can be cleared by writing a 1 to the selected bit of
I/O port 0xED0h.
Sleep S4
1 = reset asserted
0 = no reset
PwrGood 1.8V
Alwys
1 = reset asserted
PwrGood 1.0V Alwys
1 = reset asserted
0 = no reset
PwrGood 5V
Alwys
1 = reset asserted
RSM Reset
1 = reset asserted
0 = no reset
PwrGood 1.5V
Alwys
1 = reset asserted
PwrGood 3.3V Alwys
1 = reset asserted
0 = no reset
Main 5V Power
1 = reset asserted
0 = no reset
Table 45 Reset and Event Status I/O Address ED0h - Read Access
D7 D6 D5 D4 D3 D2 D1 D0
PwrGood 1.05V
1 = reset asserted
0 = no reset
Pwr Good Vcore
1 = reset asserted
0 = no reset
Sleep S3
1 = reset asserted
0 = no reset
PwrGood 1.2V
Alwys
1 = reset asserted
PwrGood 1.0V
1 = reset asserted
0 = no reset
PwrGood Vgfx
1 = reset asserted
0 = no reset
PwrGood 1.9V Alwys
1 = reset asserted
0 = no reset
Memory Pwr
Good
1 = reset asserted
Table 46 Reset and Event Status I/O Address ED1h - Read Access
D7 D6 D5 D4 D3 D2 D1 D0