BDM-610000075
Rev B
Chapter 4: Using the cpuModule
71
CUR_SGT_ROW
: The current row in the Scatter-Gather Table that will be used for the next transfer. This is the
same value for every channel, i.e. the channels are always synchronized.
Channel Gain Table Registers
The registers described in this section are paged based on the value of SELECT[CGT_CHANNEL] in on page 69.
These can be though of as rows in a scan table, each associated with a specific A/D channel. When a scan is
started (either by the pacer clock or a software trigger), channel 1 is sampled. Then the “NEXT_CHANNEL”
pointer is followed to select the next channel to scan. The “NEXT_CHANNEL” pointer is followed until it is a
value of 0, which ends the scan. There are a few implications:
1.
The first channel to be scanned must always be Channel 1.
2.
Each channel may only be sampled once per scan.
3.
The scan list must end with a “NEXT_CHANNEL” of 0. Otherwise the channels will continue to scan
without waiting for the pacer clock.
The channel associations for CGT_CHANNEL and NEXT_CHANNEL are shown below.
0x9EA: CUR_SGT_ROW
Register
Bit
7
6
5
4
3
2
1
0
Mode
R
R
Default
0
0
Field
Reserved
CUR_SGT_ROW
Table 52
Channel Gain Table Channels
CGT_CHANNEL/
NEXT_CHANNEL
Value
Single Ended
Differential
0
Channel 1 (Pin 1)
Ch1(+), Ch2(-)
1
Channel 2 (Pin 2)
Ch2(+), Ch1(-)
2
Channel 3 (Pin 3)
Ch3(+), Ch4(-)
3
Channel 4 (Pin 4)
Ch4(+), Ch3(-)
4
Channel 5 (Pin 5)
Ch5(+), Ch6(-)
5
Channel 6 (Pin 6)
Ch6(+), Ch5(-)
6
Channel 7 (Pin 7)
Ch7(+), Ch8(-)
7
Channel 8 (Pin 8)
Ch8(+), Ch7(-)
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