Ross Synergy 1, Руководство по обслуживанию

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5–8 • Frame Processor (CPU) Board Synergy 1 and Synergy 100 Maintenance Guide (v16-S1)
Deserializer Module
Deserializer Modules (4000A-061) receive serial data and output parallel data, in preparation for
processing video within the MLE. A single module processes one bus. The figure below illustrates a
simplified block diagram, as the input buses are routed through a
bank of Deserializer Modules .
Refer to the section “ Block Diagram ” on page 2–2 for an expanded view.
Block Diagram — Deserializer Module
The figure below illustrates a Deserializer Module , with four chips highlighted.
Deserializer Module
1. Serial/Parallel Translation Chips
These chips provide the translation functionality from serial data to parallel data.
2. Delay Memory
This chip provides the delay memory required to handle auto timing.
3. FPGA
This chip is the flash-based FPGA that controls the deserializing process and
auto-timing requirements.
1) Serial/Parallel Translation Chip 2) Delay Memory 3) FPGA
Note All Deserializer Modules are identical. If a critical module fails (such
as Background), you can swap a module from a non-critical location
(such as an unused timed Aux Bus slot ) in order to continue
production. You can
not hot-swap modules.
8 x 40
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Bkgd
Pst
K1 Video
K2 Video
K1 Alpha
K2 Alpha
4216A-001
4000A-048
Squeeze & Tease
4000A-049
Border Generator
Program Out
Preview Out
DVE Send
Clean Feed
DVE Alpha
DVE Video
From
Input/Crosspoint
Matrix
1 3 2