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Using PEEDI
Description:
This describes which PIOs are dedicated to the SPI SPCK, MISO and MOSI signals.
Used when describing Atmel DataFlash. If the CPU parameter is set to BF5XX, only
SPI_CS is accepted and expects 1..7, which corresponds to FLG1-FLG7.
See Blackfin’s SPI_FLG.
Example:
SPI_SPCK = PIOA, A, 2
SPI_MISO = PIOA, A, 0
SPI_MISO = PIOA, A, 1
SPI_CS = PIOA, A, 3
CMD_BASE
Synopsis:
CMD_BASE = <address>
Description:
Base address, that if written to, the NAND CLE signal will be asserted. On MPC83XX
devices with built-in NAND FLASH controller this parameter tells PEEDI the offset of
Internal Memory Mapped Registers, i.e. value of IMMRBAR.
DATA_BASE
Synopsis:
DATA_BASE = Address
Description:
Base address, that if written to, the NAND ALE and CLE signals will be inactive. On
MPC83XX devices with built-in NAND FLASH controller this parameter tells PEEDI
the address of the data buffer used by NAND FLASH controller.
ADDR_BASE
Synopsis:
ADDR_BASE = <address>
PEEDI User’s Manual
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