Rohde & Schwarz R&S SMU200A, Руководство по обслуживанию

Страница: 138 / 294

R&S SMU200A Instrument Design and Function Description
1007.9845.82 3.11 E-6
Universal Coder UNICOD
A maximum of two of these modules can be fitted in the instrument, depending on the instrument
configuration. If no Fading Simulator (option B14) is installed, the Universal Coder modules must be
inserted directly next to the DAC Interface (slot 5 and 4, X150 and X140). If the module is inserted
nearer to the front, the I/Q data flow in the baseband will be interrupted!
Two-path instruments only:
The module installed closest to the DAC Interface is referred to as Universal Coder1 and is
responsible for modulation in Path A. The module closest to the front is referred to as Universal
Coder2 and is responsible for modulation in Path B.
The Universal Coder module provides the following functions:
-
Receiving of external modulation data or generation of modulation data (either PRBS, patterns, list
…)
-
Encoding and modulation of this data (depending on selected code, e.g. QPSK) at the desired
symbol rate.
-
Filtering of the modulation symbols (e.g. root cosine)
-
Conversion of the clock rate at the symbol level to the clock rate of the converter.
-
Addition of an arbitrary waveform generator signal either to the symbol level or to the output signal.
-
Level adjustment of the generated signal in the baseband.
-
Injection (depending on the selected signal path setting) of the generated signal into the baseband
data flow for I and Q.
-
Generation of marker signals. They go directly from the Universal Coder to the outputs.
The following signal processing blocks are provided in the Universal Coder in order to permit these
functions:
-
Bus interface (FPGA “PSD”): Forms the connection with the PCI bus and monitors the functioning of
the SDRAM (for lists and arbitrary waveform). All adjustment procedures run via this interface.
-
SDRAM: The lists (modulation data) and waveforms are stored here. The memory is always
operated at the same clock rate (approx. 101 MHz) irrespective of the selected symbol rate.
-
DSP: Manages the modulation sources and actuates the respective modules in the case of complex
scenarios (e.g. 3GPP or GSM).
-
Code-FPGA: Useful bits are encoded into actual I and Q values here. Depending on the desired
encoding, a different version is in some cases loaded to this FPGA. At present, there are COD_D
(for DIGMOD such as GSM) and COD_W (for 3GPP and so on). The Code-FPGA uses an external
memory for storing individual symbols.
-
Clock converter: This consists of two special chips, DUC and RESAMPLER. The DUC chip converts
the clock rate by an integer multiple and the RESAMPLER chip by any given rational ratio. As a
result, the converter clock rate can always remain at 100 MHz irrespective of the symbol rate.
-
Signal output stage (FPGA “ROUT”): Here the I-Q data which comes from the resampler with a
sampling rate of 100 MHz undergoes level adjustment and is injected into the data flow of the
baseband.
-
Clock generation: An adjustable symbol reference of 400 Hz to approx. 80 MHz is generated from
the reference supply of the baseband (100 MHz). A VCO which is set in the range 110 to 250 MHz is
used for this purpose. The bandwidth of the loop filter can be switched in stages so that steady-state
operation can be achieved at different speeds according to requirements. The phase comparators
and clock dividers are located in the FPGA “CLOCK”.