Rockwell Automation 2080-L50E-24AWB, Руководство пользователя, Страница: 222 / 390

222 Rockwell Automation Publication 2080-UM002N-EN-E - November 2022
Chapter 10 Use the High-Speed Counter and Programmable Limit Switch
The MH (High Preset Mask) control bit is used to enable (allow) or disable (not allow) a high
preset interrupt from occurring. If this bit is clear (0), and a High Preset Reached condition is
detected by the HSC, the HSC user interrupt is not executed.
This bit is controlled by the user program and retains its value through a power cycle. It is up
to the user program to set and clear this bit.
The ML (Low Preset Mask) control bit is used to enable (allow) or disable (not allow) a low preset
interrupt from occurring. If this bit is clear (0), and a Low Preset Reached condition is detected
by the HSC, the HSC user interrupt is not executed.
This bit is controlled by the user program and retains its value through a power cycle. It is up
to the user program to set and clear this bit.
HSC Interrupt Status
Information
The Enabled bit is used to indicate HSC interrupt enable or disable status.
The EX (User Interrupt Executing) bit is set (1) whenever the HSC sub-system begins processing
the HSC subroutine due to any of the following conditions:
• Low preset reached
• High preset reached
• Overflow condition – count up through the overflow value
• Underflow condition – count down through the underflow value
The HSC EX bit can be used in the control program as conditional logic to detect if an HSC
interrupt is executing.
The HSC sub-system will clear (0) the EX bit when the controller completes its processing of
the HSC subroutine.
Mask for IH (HSC0.MH)
Description Data Format
HSC Modes
(1)
(1) For Mode descriptions, see Count Down (HSCSTS.CountDownFlag) on page 211 .
User Program Access
MH - High Preset Mask bit 0…9 read only
Mask for IL (HSC0.ML)
Description Data Format
HSC Modes
(1)
(1) For Mode descriptions, see Count Down (HSCSTS.CountDownFlag) on page 211 .
User Program Access
ML - Low Preset Mask bit 2…9 read only
User Interrupt Enable (HSC0.Enabled)
Description Data Format
HSC Modes
(1)
(1) For Mode descriptions, see Count Down (HSCSTS.CountDownFlag) on page 211 .
User Program Access
HSC0.Enabled bit 0…9 read only
User Interrupt Executing (HSC0.EX)
Description Data Format
HSC Modes
(1)
(1) For Mode descriptions, see Count Down (HSCSTS.CountDownFlag) on page 211 .
User Program Access
HSC0.EX bit 0…9 read only
User Interrupt Pending (HSC0.PE)
Description Data Format
HSC Modes
(1)
(1) For Mode descriptions, see Count Down (HSCSTS.CountDownFlag) on page 211 .
User Program Access
HSC0.PE bit 0…9 read only