Section 28 Power-Down Modes
Rev. 0.50 May 18, 2006 Page 1378 of 1588
REJ09B0313-0050
Bit Bit
Name
Initial
Value
R/W Description
2
RAMWE2
1
R/W
RAM Write Enable 2 (corresponding area of on-chip
RAM (high-speed): page 2
*
)
0: Write to on-chip RAM (high-speed) disabled
1: Write to on-chip RAM (high-speed) enabled
1
RAMWE1
1
R/W
RAM Write Enable 1 (corresponding area of on-chip
RAM (high-speed): page 1
*
)
0: Write to on-chip RAM (high-speed) disabled
1: Write to on-chip RAM (high-speed) enabled
0
RAMWE0
1
R/W
RAM Write Enable 0 (corresponding area of on-chip
RAM (high-speed): page 0
*
)
0: Write to on-chip RAM (high-speed) disabled
1: Write to on-chip RAM (high-speed) enabled
Note:
*
For addresses in each page, see section 27, On-Chip RAM.
28.2.9
System Control Register 3 (SYSCR3)
SYSCR3 is an 8-bit readable/writable register that performs the software reset control for the SSI0
to SSI3. Only byte access is valid.
Note: When writing to this register, see section 28.4, Usage Notes.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
R
R
R
R/W
R/W
R/W
R/W
Bit:
Initial value:
R/W:
-
-
-
-
SSI3
SRST
SSI2
SRST
SSI0
SRST
SSI1
SRST
Bit Bit
Name
Initial
Value
R/W Description
7 to 4
All
0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
3
SSI3SRST
0
R/W
SSI3 Software Reset
Controls the SSI3 reset by software
0: Cancels the SSI3 reset.
1: Puts the SSI3 in the reset state.
Содержание Single-Chip Microcomputer SH7203
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Страница 1598: ...Section 31 Electrical Characteristics Rev 0 50 May 18 2006 Page 1568 of 1588 REJ09B0313 0050 ...
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