Renesas RL78/G1H, Руководство пользователя

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RL78/G1H CHAPTER 7 TIMER ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 175 of 920
Dec 22, 2016
7.5 Operation of Counter
7.5.1 Count clock (f
TCLK
)
The count clock (f
TCLK
) of the timer array unit can be selected between following by CCSmn bit of timer mode
register mn (TMRmn).
• Operation clock (f
MCK
) specified by the CKSmn0 and CKSmn1 bits
• Valid edge of input signal input from the TImn pin
Because the timer array unit is designed to operate in synchronization with f
CLK
, the timings of the count clock
(f
TCLK
) are shown below.
(1) When operation clock (f
MCK
) specified by the CKSmn0 and CKSmn1 bits is selected (CCSmn = 0)
The count clock (f
TCLK
) is between f
CLK
to f
CLK
/2
15
by setting of timer clock select register m (TPSm). When
a divided f
CLK
is selected, however, the clock selected in TPSmn register, but a signal which becomes high
level for one period of f
CLK
from its rising edge. When a f
CLK
is selected, fixed to high level.
Counting of timer count register mn (TCRmn) delayed by one period of f
CLK
from rising edge of the count
clock, because of synchronization with f
CLK
. But, this is described as “counting at rising edge of the count
clock”, as a matter of convenience.
Figure 7 - 26 Timing of f
CLK
and count clock (f
TCLK
) (When CCSmn = 0)
Remark 1. : Rising edge of the count clock
: Synchronization, increment/decrement of counter
Remark 2. f
CLK
: CPU/peripheral hardware clock
f
CLK
f
CLK
/2
f
CLK
/4
f
CLK
/8
f
CLK
/16
f
TCLK
( = f
MCK
= CKmn)