Renesas RA Family
RA2 Quick Design Guide
R01AN6060EU0100 Rev.1.00
Page 19 of 44
Sep.14.21
6.5 Voltage-Monitoring Resets
The RA2 MCU family includes circuitry that allows the MCU to protect against unsafe operation during
brownouts. On-board comparators check the supply voltage against three reference voltages, V
det0
, V
det1
,
and V
det2
. As the supply dips below each reference voltage an interrupt or a reset can be generated. The
detection voltages V
det0
, V
det1
, and V
det2
are each selectable from 3 different levels.
When VCC subsequently rises above V
det0
, V
det1
, or V
det2
, release from the voltage-monitoring reset proceeds
after a stabilization time has elapsed.
Low Voltage Detection is disabled after a power on reset. Voltage monitoring can be enabled by using the
Option Function register OFS1. For more details, see the chapter “Low Voltage Detection (LVD)” in the
Hardware User’s Manual.
After an LVD Reset, the LVDnRF (n = 0, 1, 2) bit in RSTSR0 is set to 1.
6.6 Software Reset
The software reset is an internal reset generated by a software setting of the SYSRESETREQ bit in the
AIRCR register in the Arm core. When the SYSRESETREQ bit is set to 1, a software reset is generated.
When the internal reset time (tRESW2) elapses after the software reset is generated, the internal reset is
canceled and the CPU starts the reset exception handling. Refer to MCU User’s Manual for the specific
timing.
For details on the SYSRESETREQ bit, see the ARM® Cortex®-M23 Technical Reference Manuals.
6.7 Other Resets
Most peripheral functions within the MCU can generate a reset under specific fault conditions. No hardware
configuration is required to enable these resets. Refer to the relevant chapters in the Hardware User’s
Manual for details of the conditions that will generate a reset for each peripheral function.
6.8 Determination of Cold/Warm Start
The RA2 MCUs allow the user to determine the cause of the reset processing. The CWSF flag in RSTSR2
indicates whether a power on reset caused the reset processing (cold start) or a reset signal input during
operation caused the reset processing (warm start.)
The flag is set to 0 when a power on reset occurs. Otherwise, the flag is not set to 0. The flag is set to 1
when 1 is written to it through software. It is not set to 0 even when 0 is written to it.
6.9 Determining the Reset Source
The RA2 MCUs allow the user to determine the reset signal generation source. Read RSTSR0, RSTSR1,
and RSTSR0 to determine which reset was the source of the reset. Refer to the Hardware User’s Manual
section “Determination of Reset Generation Source” for the flow diagram.
The following sample code shows how to determine if a reset is caused by Power On Reset or Software
Reset using CMSIS based register structure in Renesas FSP.
/* Power on Reset */
if(1 == R_SYSTEM->RSTSR0_b.PORF)
{
/* Do something */
}
/* Software Reset */
if(1 == R_SYSTEM->RSTSR1_b.SWRF)
{
/* Do something */
}
