R01UH0092EJ0110 Rev.1.10
Page 224 of 807
Jul 31, 2012
M16C/64C Group
15. Watchdog Timer
15. Watchdog Timer
15.1
Introduction
The watchdog timer contains a 15-bit counter, and the count source protection mode (enabled/disabled)
can be set.
Table 15.1 lists Watchdog Timer Specifications.
Refer to 6.4.8 “Watchdog Timer Reset”
for details of watchdog timer reset.
Figure 15.1 shows Watchdog Timer Block Diagram.
Figure 15.1
Watchdog Timer Block Diagram
Table 15.1
Watchdog Timer Specifications
Item
Count Source Protection Mode Disabled
Count Source Protection Mode Enabled
Count source
CPU clock
fOCO-S
Count operation
Decrement
Count start conditions
Either of the following can be selected
(selected by the WDTON bit in the OFS1 address)
•
Count automatically starts after reset.
•
Count starts by writing to the WDTS register.
Count stop condition
Stop mode, wait mode, bus hold
None
Watchdog timer
counter refresh
timing
•
Reset (refer to 6. “Resets”)
•
Write 00h, and then FFh to the WDTR register.
•
Underflow
Operation when the
timer underflows
Watchdog timer interrupt or watchdog
timer reset
Watchdog timer reset
Selectable functions
•
Prescaler divide ratio
Divide-by-16 or divide-by-128 (selected by the WDC7 bit in the WDC register)
However, divide-by-2 is selected when the CM07 bit in the CM0 register is 1
(sub clock).
•
Count source protection mode
Enabled or disabled (selected by the CSPROINI bit in the OFS1 address and
the CSPRO bit in the CSPR register)
1/128
1/2
Watchdog timer counter
CPU clock
CM07
Prescaler
CSPRO
1/16
WDC7
fOCO-S
Write to the WDTR register
b14
b0
Internal reset signal
(low active)
WDTR register written
WDTON bit in the OFS1 address
Watchdog timer reset
Watchdog timer
interrupt
PM12
b10
b3
0
1
Refresh
Underflow
WDC4 to WDC0
0
1
Bus hold
0
1
0
1
WDC7,WDC4 to WDC0: Bits in the WDC register
CSPRO: Bit in the CSPR register
CM07: Bit in the CM0 register
PM12: Bit in the PM register
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