Renesas 89HPES24T3G2ZBAL, Руководство пользователя

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IDT Configuration Registers
PES24T3G2 User Manual 8 - 67 February 22, 2012
Notes
GPESTS - General Purpose Event Status (0x454)
SERDESCTL- SerDes Control (0x500)
4 P4GPEE RW 0x0
Sticky
Port 4 General Purpose Event Enable. When this bit is set, the
hot-plug INTx, MSI and PME event notification mechanisms
defined by the PCIe base 2.0 specification are disabled for port 4
and are instead signalled through General Purpose Event
(GPEN) signal assertions. GPEN is an alternate function of
GPIO[7].
31:5 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description
1:0 Reserved RO 0x0 Reserved field.
2 P2GPES RO 0x0 Port 2 General Purpose Event Status. When this bit is set, the
corresponding port is signalling a general purpose event by
asserting the GPEN signal. This bit is never set if the correspond-
ing general purpose event is not enabled in the GPECTL register.
GPEN is an alternate function of GPIO[7] and GPIO[7] is
asserted only if enabled to operate as an alternate function.
3 Reserved RO 0x0 Reserved field.
4 P4GPES RO 0x0 Port 4 General Purpose Event Status. When this bit is set, the
corresponding port is signalling a general purpose event by
asserting the GPEN signal. This bit is never set if the correspond-
ing general purpose event is not enabled in the GPECTL register.
GPEN is an alternate function of GPIO[7] and GPIO[7] is
asserted only if enabled to operate as an alternate function.
31:5 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description
7:0 Reserved RO 0x0 Reserved field.
8 LSE RW 0x0
Sticky
Low-Swing Mode Enable. When set, this bit enables Low-Swing
mode operation at the SerDes Transmit logic. Please refer to
section Low-Swing Transmitter Voltage Mode on page 3-10 for
further details.
0x0 - Full-Swing Mode
0x1 - Low-Swing Mode
31:9 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description