Ameba-D User Manual
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392
Bit
Name
Access
Reset
Description
31:0
SP_RX_DR
R
32’h0
It’s Rx data window between SW/GDMA and SPORT.
18.4.1.6
SP_FIFO_SR
Name
: SPORT FIFO status register
Size
: 32 bits
Address offset
: 0x0014
Read/write access
: read
31
30
29
28
27
26
25
24
RX1_RCNT_BUS
R
23
22
21
20
19
18
17
16
RX0_RCNT_BUS
R
15
14
13
12
11
10
9
8
TX1_WCNT_BUS
R
7
6
5
4
3
2
1
0
TX0_WCNT_BUS
R
Bit
Name
Access
Reset
Description
31:24
RX1_RCNT_BUS
R
8’h0
Rx1 FIFO read counter status (MIC path)
23:16
RX0_RCNT_BUS
R
8’h0
Rx0 FIFO read counter status (MIC path)
15:8
TX1_WCNT_BUS
R
8’h0
Tx1 FIFO write counter status (SPK path)
7:0
TX0_WCNT_BUS
R
8’h0
Tx0 FIFO write counter status (SPK path)
18.4.1.7
SP_ERROR_CNT_SR
Name
: SPORT error counter register
Size
: 32 bits
Address offset
: 0x0018
Read/write access
: read
31
30
29
28
27
26
25
24
RSVD
23
22
21
20
19
18
17
16
RSVD
15
14
13
12
11
10
9
8
RX_ERR_CNT
R
7
6
5
4
3
2
1
0
TX_ERR_CNT
R
Bit
Name
Access
Reset
Description
31:16
RSVD
N/A
16’h0
Reserved
15:8
RX_ERR_CNT
R
8’h0
Rx error counter (MIC path)
Note
: This counter should always be zero if everything works well.
7:0
TX_ERR_CNT
R
8’h0
Tx error counter (SPK path)
Note
: This counter should always be zero if everything works well.
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2019-05-15 10:08:03