Remote Control
R&S
®
ZNC
351
User Manual 1173.9557.02 ─ 13
SRE
STB
STATus:OPERation Register
PPE
IST flag
(answer to parallel poll)
& = logical AND
= logical OR
of all bits
ESE
ESR
Error Queue Output Buffer
SRQ
RQS/MSS
ESB
MAV
Power on
User request
Command error
Execution error
Device-dependent error
Query error
not used
Operation complete
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
7
6
5
4
3
2
1
0
STATus:QUEStionable Register
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
LIMit1 summary
INTegrity summary
not used
not used
not used
not used
not used
not used
not used
not used
not used
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
STATus:QUEStionable
:LIMit1 Register
not used
Limit trace no. 14
Limit trace no. 13
Limit trace no. 12
Limit trace no. 11
Limit trace no. 10
Limit trace no. 9
Limit trace no. 8
Limit trace no. 7
Limit trace no. 6
Limit trace no. 5
Limit trace no. 4
Limit trace no. 3
Limit trace no. 2
Limit trace no. 1
LIMit2 summary
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
STATus:QUEStionable
:LIMit2 Register
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
Limit trace no. 16
Limit trace no. 15
not used
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
STATus:QUEStionable:INTegrity Register
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
not used
HARDware summary
not used
not used
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
-&-
STATus:QUEStionable
:INTegrity:HARDware Register
Detector meas. time limited
Port power settings exceed limits
Overload at DC MEAS
Time grid too close
Problem conc. external power meter
not used
not used
Oven cold
Instr. temperature too high
Internal communication error
not used
not used
Receiver overload
Output power unleveled
Ref. frequency lock failure
not used
5.5.2 Structure of an SCPI Status Register
Each standard SCPI register consists of 5 parts which each have a width of 16 bits and
have different functions. The individual bits are independent of each other, i.e. each
hardware status is assigned a bit number which is valid for all five parts. Bit 15 (the most
significant bit) is set to zero for all parts. Thus the contents of the register parts can be
processed by the controller as positive integer.
Status Reporting System