Protocol analysis
R&S
®
RTO6
892
User Manual 1801.6687.02 ─ 05
13.24.1
M-PHY basic
This chapter provides an overview of the characteristics of the M-PHY and UniPro pro-
tocols.
13.24.1.1
Data transfer
M-PHY words are always 10 bits long (both data and control words). For UniPro, they
have variable lengths that depend on the frame type. For example, control words have
8 bits, data words have 16 bits and reserved words have 3 bits.
To achieve power efficiency and high-performance transmissions, multiple power-sav-
ing states and recovery times are utilized. Scalability and flexibility are achieved
through the various transmission speed ranges and rates.
Different modes of operations:
●
Disable mode: lowest power mode entered into once the power supply is turned on
●
Hibernate (Hibern8): ultra low-power state, which can be used without configura-
tion loss
●
High-speed mode (HS): supports three gears with predefined data rates. This
mode is used during high-speed transmission for transporting large volume of data.
This mode utilizes the power-saving Stall state to reduce power consumption while
offering a fast state transition in the range of nanoseconds
●
Low-power mode (PWM): supports seven gears with predefined frequency ranges.
This mode is used during low-speed transmission for power conservation. This
mode utilizes the power-saving Sleep state with a state transition time typically in
the range of microseconds
The R&S
RTO6 supports all operating speed modes: high-speed and low-power mode.
The gear settings of these modes are auto detected by the instrument.
13.24.1.2
Data analysis
The M-PHY and UniPro decoding process involves several stages, similar to D-PHY.
The stages are as the following:
●
Stage 1: involves two substages:
–
Stage 1a: converts the three stage cross points into bit and attempts a HS-
Sync. This stage involves the Hibern8-Detection/Filter, NRZ Unclocked
Decoder and Burst Detection.
–
Stage 1b is only involved if Stage 1a burst detection fails, assuming using
PWM. Input is from the bits from stage 1a. This stage involves the PWM
Decoder, Line CFG Decoder and Burst Detection.
●
Stage 2: performs the 8b/10b decoding of bits from stage 1 into Bytes and identi-
fies the 8b/10b control words. This stage involves the 8b/10b Decoder and Shift-
decoder to Bytes.
●
Stage 3: starts decoding the Bytes from stage 2. This stage involves the Descram-
bler and 17-bit Shift Decoder.
M-PHY and USB SSIC (option R&S
RTO6-K580 and K570)
