R&S 1311.6010K22, Руководство пользователя

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Remote control
R&S
®
ZNB/ZNBT
830 User Manual 1173.9163.02 ─ 62
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The
STATus:QUEStionable:LIMit<1|2>
register indicates the result of the
limit check.
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The
STATus:QUEStionable:INTegrity
register monitors hardware failures of
the analyzer.
6.5.3.1 STB and SRE
The STatus Byte (STB) provides a rough overview of the instrument status by collect-
ing the pieces of information of the lower registers. The STB represents the highest
level within the SCPI hierarchy. A special feature is that bit 6 acts as the summary bit
of the remaining bits of the status byte.
The STB is linked to the Service Request Enable (SRE) register on a bit-by-bit basis.
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The STB corresponds to the EVENt part of a SCPI register, indicating the current
instrument state. This register is cleared when it is read.
●
The SRE corresponds to the ENABle part of a SCPI register. If a bit is set in the
SRE and the associated bit in the STB changes from 0 to 1, a
Service request
(SRQ) is generated. Bit 6 of the SRE is ignored, because it corresponds to the
summary bit of the STB.
The bits in the STB are defined as follows:
Bit No. Meaning
2 Error queue not empty
If this bit is enabled by the SRE, each entry of the error queue generates a Service
request (SRQ). Thus an error can be recognized and further pinned down by polling the
error queue. The poll provides an informative error message.
3 QUEStionable status summary bit
This bit is set if an EVENt bit is set in the STATus:QUEStionable register and the associ-
ated ENABle bit is set to 1.
The bit indicates a questionable instrument status, which can be further pinned down by
polling the QUEStionable register.
4 MAV bit (message available)
This bit is set if a message is available and can be read from the output buffer.
This bit can be used to transfer data from the instrument to the controller automatically.
5 ESB bit
Sum bit of the event status register. It is set if one of the bits in the event status register is
set and enabled in the event status enable register.
Setting of this bit implies an error or an event which can be further pinned down by polling
the event status register.
6 MSS bit (master status summary bit)
This bit is set if the instrument triggers a service request, which happens if one of the other
bits of this register is set together with its mask bit in the SRE register.
7 OPERation status register summary bit
This bit is set if an EVENt bit is set in the OPERation status register and the associated
ENABle bit is set to 1.
The bit indicates that the instrument is performing an action. The type of action can be
determined by polling the
STATus:OPERation register.
Status reporting system