RadiSys P3000BX2 Series, Руководство по обслуживанию

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Technical Data
Service Manual EPC-2322 SBC (P3000(D)BX2 Series) 39
Watchdog Timer
Overview
The watchdog timer provides an escape from a system lockup caused by electrical
noise, electrostatic discharge, power failure, software hang-up, etc. The watchdog
provides the escape by performing a reset of all system components.
Reset
Once the watchdog timer detects an activity pulse, an internal timer begins to count
down from the preset time delay, either 150 milliseconds or 1.2 seconds. If the
watchdog counts down to zero before it detects another pulse, it will perform a reset.
This, in turn, issues a reset to the PCI and ISA busses, thereby resetting the devices
installed on the busses.
Control
Two features control the watchdog timer operations: Status and Delay. These options
are defined in the Setup Utility. See
page 25 .
• Watchdog Status : sets the source of the activity monitored by the watchdog timer.
•
Enabled: the source of the pulse is the CPU Address Strobe (ADS) line.
•
Disabled: the source of the pulse is the CPU system clock.
• Watchdog Delay : sets the amount of time in which the system will be monitored
for activity, either 150 milliseconds or 1.2 seconds.
User Mode
In addition to the Setup Utility features, there is a User mode to control the watchdog
timer operations. A user-controlled bit can be used to block the activity pulse from the
watchdog timer. If the control bit is set, the user-defined application must clear the bit
within the designated time to prevent a reset.
For more information, contact Technical Support. See “Customer Support,” page vi .
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