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Chapter 26 Low-Power Operation
281
Global Power Save Control Register
(GPSCR)
(Address = 0x000D)
Bit(s)
Value
Description
7:5
000
Self-timed chip selects are disabled.
001
230 ns self-timed chip selects for read and write.
010
170 ns self-timed chip selects for read and write.
011
110 ns self-timed chip selects for read and write.
100
290 ns self-timed chip selects for read only.
101
230 ns self-timed chip selects for read only.
110
170 ns self-timed chip selects for read only.
111
110 ns self-timed chip selects for read only.
4
0
Normal chip select timing for read cycles.
1
Short chip select timing for read cycles (not available in full speed).
3
0
Normal chip select timing for write cycles
1
Short chip select timing for write cycles (not available in full speed).
2:0
000
The 32 kHz clock divider is disabled.
001
This bit combination is reserved and should not be used.
010
This bit combination is reserved and should not be used.
011
This bit combination is reserved and should not be used.
100
32 kHz clock divided by 2 (16.384 kHz).
101
32 kHz clock divided by 4 (8.192 kHz).
110
32 kHz clock divided by 8 (4.096 kHz).
111
32 kHz clock divided by 16 (2.048 kHz).
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