UMTS/HSPA(+) Module Series
UC200T-EM Hardware Design
UC200T-EM_Hardware_Design 37 / 68
Clock and mode can be configured by AT command, and the default configuration is master mode using
short frame synchronization format with 2048kHz PCM_CLK and 8kHz PCM_SYNC. Please refer to
document [2]
for more details about
AT+QDAI
command.
The following figure shows a reference design of PCM interface with external codec IC.
PCM_IN
PCM_OUT
PCM_SYNC
PCM_CLK
I2C_SCL
I2C_SDA
Module
1.8V
4
.7
K
4
.7
K
BCLK
LRCK
DAC
ADC
SCL
SDA
B
IA
S
MICBIAS
INP
INN
LOUTP
LOUTN
Codec
Figure 16: Reference Circuit of PCM Application with Audio Codec
1. It is recommended to reserve an RC (R=22ohm, C=22pF) circuit on the PCM lines, especially for
PCM_CLK.
2. UC200T-EM works as a master device pertaining to I2C interface.
PCM_CLK
27
IO
PCM data bit clock
1.8V power domain
Output when module works as
master mode
Intput when module works as
salve mode
If unused, keep it open.
I2C_SCL
41
OD
I2C serial clock
Require external pull-up to 1.8V.
If unused, keep it open.
I2C_SDA
42
OD
I2C serial data
Require external pull-up to 1.8V.
If unused, keep it open.
NOTES