SA800U-WF
Hardware Design
Smart Module Series
Version: 1.0
Date: 2021-01-13
Status: Released
www.quectel.com
Страница 1: ...SA800U WF Hardware Design Smart Module Series Version 1 0 Date 2021 01 13 Status Released www quectel com ...
Страница 2: ...ior notice Disclaimer While Quectel has made efforts to ensure that the functions and features under development are free from errors it is possible that these functions and features could contain errors inaccuracies and omissions Unless otherwise provided by valid agreement Quectel makes no warranties of any kind implied or express with respect to the use of features and functions under developme...
Страница 3: ...f Quectel Transmitting reproducing disseminating and editing this document as well as using the content without permission are forbidden Offenders will be held liable for payment of damages All rights are reserved in the event of a patent grant or registration of a utility model or design Copyright Quectel Wireless Solutions Co Ltd 2021 All rights reserved ...
Страница 4: ...s may cause interference on sensitive medical equipment so please be aware of the restrictions on the use of wireless devices when in hospitals clinics or other healthcare facilities Cellular terminals or mobiles operating over radio signal and cellular network cannot be guaranteed to connect in certain conditions such as when the mobile bill is unpaid or the U SIM card is invalid When emergency h...
Страница 5: ...dware Design SA800U WF_Hardware_Design 4 106 About the Document Revision History Version Date Author Description 2020 07 31 Light WANG Finley ZHANG Creation of the document 1 0 2021 01 13 Light WANG Finley ZHANG First official release ...
Страница 6: ...ease Voltage Drop 38 3 4 3 Reference Design for Power Supply 39 3 5 Turn on and off Scenarios 40 3 5 1 Turn on the Module Using PWRKEY 40 3 5 2 Turn on the Module Automatically Using CBL_PWR_N 42 3 5 3 Turn off Restart the Module 43 3 6 VRTC Interface 43 3 7 Power Output 44 3 8 Battery Charging and Management 45 3 9 USB Interfaces 48 3 9 1 USB1 Interface 48 3 9 1 1 USB Type C Mode 48 3 9 1 2 Displ...
Страница 7: ...enna Connection 86 5 1 Antenna Connectors 86 5 2 Antenna Installation 87 5 2 1 Antenna Requirements 87 5 2 2 Recommended Mating Plug for Antenna Connection 88 6 Reliability Radio and Electrical Characteristics 90 6 1 Absolute Maximum Ratings 90 6 2 Power Supply Ratings 90 6 3 Operating and Storage Temperatures 91 6 4 Current Consumption 91 6 5 Electrostatic Discharge 93 6 6 Thermal Dissipation 93 ...
Страница 8: ... 19 Pin Definition of ADC Interfaces 62 Table 20 Pin Definition of Vibrator Drive Interface 62 Table 21 Pin Definition of LCM Interfaces 63 Table 22 Pin Definition of Touch Panel Interface 67 Table 23 Pin Definition of Camera Interfaces 68 Table 24 CSI Data Rate and PCB Maximum Trace Length D PHY 73 Table 25 DSI Data Rate and PCB Maximum Trace Length D PHY 74 Table 26 MIPI Trace Length Inside the ...
Страница 9: ...Smart Module Series SA800U WF Hardware Design SA800U WF_Hardware_Design 8 106 Table 42 Tray Package 101 Table 43 Related Documents 102 Table 44 Terms and Abbreviations 102 ...
Страница 10: ... Figure 19 PCIe Interfaces Reference Circuit 56 Figure 20 Reference Circuit for SD Card Interface 58 Figure 21 Reference Circuit for Vibrator Connection 63 Figure 22 Reference Circuit Design for LCM0 Interface 65 Figure 23 Reference Circuit Design for LCM1 Interface 66 Figure 24 Reference Design of LCM1 External Backlight Driving Circuit 67 Figure 25 Reference Circuit Design for Touch Panel Interf...
Страница 11: ...ule and describes its air interfaces and hardware interfaces This document helps you quickly understand module interface specifications electrical and mechanical details as well as other related information of the module Associated with application notes and user guides you can use the module to design and set up applications easily ...
Страница 12: ...d low power Snapdragon sensor core DSP to support always on use cases Provide multiple audio and video input output interfaces as well as abundant GPIO interfaces The following table shows the supported frequency bands of the module Table 1 SA800U WF Frequency Bands SA800U WF is a 396 pin module which supports B2B connection With a compact profile of 60 0 mm 37 0 mm 6 55 mm the module can meet alm...
Страница 13: ...4 4 V Typ 3 8 V WLAN Features 2 4 5 GHz 802 11a b g n ac Support 2 2 MIMO maximally up to 866 Mbps Support AP and STA modes Bluetooth Features BT 2 1 EDR 3 0 4 1 LE 4 2 BLE BT 5 0 LCM Interfaces Support two groups of 4 lane MIPI DSI Support dual LCDs Support 2560 1600 60 fps VESA DSC 1 1 primary display with 4 lanes Support 4K 60 fps over DisplayPort Provide one high voltage output for powering st...
Страница 14: ...complies with SD 3 0 specifications I2C Interfaces 6 I2C interfaces used for peripherals such as TP camera sensor etc I2S Interfaces 3 I2S interfaces Flashlight Interfaces 3 high current flash LED drivers which supports both flash and torch modes Up to 1 5 A for FLASH_LED1 FLASH_LED2 in flash mode Up to 0 75 A for FLASH_LED3 in flash mode ADC Interfaces 2 general purpose ADC interfaces SPI Interfa...
Страница 15: ... Functional Diagram The following figure shows a block diagram of SA800U WF and illustrates the major functional parts Power management Baseband LPDDR4X UFS flash Peripheral interfaces USB interfaces PCIe interfaces UART interface I2C interfaces SPI interfaces SD card interface GPIO interfaces SLIMbus interface I2S interfaces ADC interfaces Vibrator drive interface LCM MIPI interfaces TP touch pan...
Страница 16: ...4A_1V8 SD_LDO21A LVS1A_1V8 LVS2A_1V8 LDO19A_3V0 LDO24A_3V075 LDO14A_1V88 LDO28A_3V0 Audio 38 4M FM ANT RGB RGB WLED Battery Display Bias VDISP XO 38 4M 2 PCIe 2 SDIO RFFE 1 Wi Fi MIMO ANT BT ANT PDET_IN CH0 PDET_IN CH1 2 4G_TRX 2 4G_TRX 5G_TX 5G_TX 5G_RX 5G_RX VREG_BOB LDO12A_1V8 Figure 1 Functional Diagram 2 4 Evaluation Board To help you develop applications with SA800U WF conveniently Quectel s...
Страница 17: ...form The following chapters provide the detailed description of interfaces listed below Power supply VRTC interface Charging interface USB interfaces UART interface PCIe interfaces SD card interface GPIO interfaces I2C interfaces SPI interfaces ADC interfaces Vibrator drive interface LCM interfaces TP interface Camera interfaces Flashlight interfaces Sensor interfaces Audio interfaces Emergency do...
Страница 18: ... J2 18 J2 12 J2 16 J2 20 J2 26 J2 22 J2 24 J2 28 J2 34 J2 30 J2 32 J2 36 J2 42 J2 38 J2 40 J2 44 J2 50 J2 46 J2 48 J2 52 J2 58 J2 54 J2 56 J2 60 J2 66 J2 62 J2 64 J2 68 J2 74 J2 70 J2 72 J2 76 J2 82 J2 78 J2 80 J2 84 J2 86 J2 95 J2 97 J2 57 J2 99 J2 101 J2 61 J2 65 J2 59 J2 63 J2 67 J2 73 J2 69 J2 71 J2 75 J2 35 J2 77 J2 33 J2 37 J2 43 J2 39 J2 41 J2 45 J2 51 J2 47 J2 49 J2 17 J2 23 J2 19 J2 21 J2...
Страница 19: ... Input DO Digital Output DIO Digital Input Output OD Open Drain PI Power Input PO Power Output Power Supply Pin Name Pin No I O Description DC Characteristics Comment VBAT J1 159 J1 160 J1 161 J1 162 J1 163 J1 164 J1 165 J1 166 J1 167 J1 168 PI PO Power supply for the module Vmax 4 4 V Vmin 3 55 V Vnom 3 8 V Must be provided with sufficient current of up to 3 A It is suggested to use a TVS to incr...
Страница 20: ...IOmax 100 mA Power supply for IOVDD or VDD of sensors Add a 1 0 2 2 μF bypass capacitor if used If unused keep this pin open LDO12A_1V8 J3 12 PO 1 8 V output Vnom 1 8 V IOmax 300 mA Connect this pin to SHDN of SMB1355 parallel charger to make the charger enter low power mode If SMB1355 is unused keep this pin open LDO14A_1V88 J4 9 PO 1 8 V output Vnom 1 8 V IOmax 50 mA Power supply for IOVDD of TP...
Страница 21: ...80 J1 83 J1 89 J1 93 J1 94 J1 97 J1 101 J1 105 J1 113 J1 119 J1 125 J1 131 J1 156 J1 157 J1 158 J2 11 J2 12 J2 17 J2 18 J2 23 J2 24 J2 29 J2 30 J2 35 J2 36 J2 41 J2 42 J2 45 J2 53 J2 98 J2 103 J2 104 J2 109 J2 110 J2 115 J2 116 J2 121 J2 122 J2 127 J2 155 J2 158 J2 161 J2 167 J3 1 J3 8 J3 13 J3 21 J3 28 J4 7 J4 12 J4 19 J4 22 J4 25 J4 28 USB Interface Pin Name Pin No I O Description DC Characteris...
Страница 22: ...eceive USB1_SS1_RX_P J2 120 AI USB1 3 1 channel 1 super speed receive USB1_SS2_TX_M J2 111 AO USB1 3 1 channel 2 super speed transmit USB1_SS2_TX_P J2 113 AO USB1 3 1 channel 2 super speed transmit USB1_SS2_RX_M J2 114 AI USB1 3 1 channel 2 super speed receive USB1_SS2_RX_P J2 112 AI USB1 3 1 channel 2 super speed receive USB_CC1 J2 141 AI USB Type C configuration channel 1 USB_CC2 J2 139 AI USB T...
Страница 23: ...USB2 3 1 channel 1 super speed receive PCIe Interfaces Pin Name Pin No I O Description DC Characteristics Comment PCIE0_RST_N J1 1 DO PCIe0 reset VOLmax 0 45 V VOHmin 1 35 V PCIE0_WAKE_N J1 3 DI PCIe0 wake up host VILmax 0 63 V VIHmin 1 17 V PCIE0_CLKREQ_N J1 5 DI PCIe0 clock request VILmax 0 63 V VIHmin 1 17 V PCIE0_REFCLK_P J1 15 AO PCIe0 reference clock Control the characteristic impedance as 8...
Страница 24: ...scription DC Characteristics Comment SDC4_CLK J1 86 DO SDIO clock VOLmax 0 45 V VOHmin 1 35 V SDIO function is not supported by default Can be multiplexed into GPIOs SDC4_CMD J1 92 DO SDIO command VOLmax 0 45 V VOHmin 1 35 V SDC4_DATA0 J1 82 DIO SDIO data bit 0 VILmax 0 63 V VIHmin 1 17 V VOLmax 0 45 V VOHmin 1 35 V SDC4_DATA1 J1 84 DIO SDIO data bit 1 SDC4_DATA2 J1 88 DIO SDIO data bit 2 SDC4_DAT...
Страница 25: ...O 1 8 2 95 V output power for SD card pull up circuits Vnom 1 8 2 95 V IOmax 50 mA TP Touch Panel Interface Pin Name Pin No I O Description DC Characteristics Comment TP_INT J2 48 DI TP interrupt VILmax 0 63 V VIHmin 1 17 V 1 8 V power domain TP_RST J2 50 DO TP reset VOLmax 0 45 V VOHmin 1 35 V TP_I2C_SCL J2 44 OD TP I2C clock TP_I2C_SDA J2 46 OD TP I2C data LCM Interfaces Pin Name Pin No I O Desc...
Страница 26: ...2 28 AO LCD0 MIPI clock DSI0_LN0_N J2 38 AO LCD0 MIPI lane 0 data DSI0_LN0_P J2 40 AO LCD0 MIPI lane 0 data DSI0_LN1_N J2 32 AO LCD0 MIPI lane 1 data DSI0_LN1_P J2 34 AO LCD0 MIPI lane 1 data DSI0_LN2_N J2 20 AO LCD0 MIPI lane 2 data DSI0_LN2_P J2 22 AO LCD0 MIPI lane 2 data DSI0_LN3_N J2 14 AO LCD0 MIPI lane 3 data DSI0_LN3_P J2 16 AO LCD0 MIPI lane 3 data DSI1_CLK_N J2 21 AO LCD1 MIPI clock DSI1...
Страница 27: ...camera 0 CSI0_LN0_N J1 22 AI MIPI lane 0 data of camera 0 CSI0_LN0_P J1 24 AI MIPI lane 0 data of camera 0 CSI0_LN1_N J1 16 AI MIPI lane 1 data of camera 0 CSI0_LN1_P J1 18 AI MIPI lane 1 data of camera 0 CSI0_LN2_N J1 10 AI MIPI lane 2 data of camera 0 CSI0_LN2_P J1 12 AI MIPI lane 2 data of camera 0 CSI0_LN3_N J1 6 AI MIPI lane 3 data of camera 0 CSI0_LN3_P J1 4 AI MIPI lane 3 data of camera 0 C...
Страница 28: ..._LN1_N J1 66 AI MIPI lane 1 data of camera 2 CSI2_LN1_P J1 64 AI MIPI lane 1 data of camera 2 CSI2_LN2_N J1 72 AI MIPI lane 2 data of camera 2 CSI2_LN2_P J1 70 AI MIPI lane 2 data of camera 2 CSI2_LN3_N J1 78 AI MIPI lane 3 data of camera 2 CSI2_LN3_P J1 76 AI MIPI lane 3 data of camera 2 CSI3_CLK_N J1 85 AI MIPI clock of camera 3 100 Ω differential impedance CSI3 can only receive data of RAW form...
Страница 29: ...e of camera 2 CAM0_RST J1 100 DO Reset of camera 0 CAM1_RST J1 96 DO Reset of camera 1 CAM2_RST J1 124 DO Reset of camera 2 CAM3_RST J1 126 DO Reset of camera 3 CAM0_PWDN J1 114 DO Power down of camera 0 CAM1_PWDN J1 120 DO Power down of camera 1 CAM2_PWDN J1 106 DO Power down of camera 2 CAM3_PWDN J1 112 DO Power down of camera 3 CAM0_AVDD_EN J1 102 DO AVDD enable of camera 0 CAM1_AVDD_EN J1 98 D...
Страница 30: ... VILmax 0 63 V VIHmin 1 17 V Pulled up to 1 8 V internally Active low VOL_UP J2 9 DI Volume up If unused keep this pin open VOL_DOWN J2 7 DI Volume down If unused keep this pin open HOME_KEY J2 145 DI Home key If unused keep this pin open Sensor Interfaces Pin Name Pin No I O Description DC Characteristics Comment SSC_I2C1_SDA J2 8 OD Sensor core I2C1 data 1 8 V power domain SSC_I2C1_SCL J2 10 OD ...
Страница 31: ...lave in SSC_SPI2_MISO J1 147 DI Sensor core SPI2 master in salve out VILmax 0 63 V VIHmin 1 17 V MAG_INT J1 133 DI Magnetic sensor interrupt MAG_DRDY_INT J1 135 DI Magnetic sensor DRDY interrupt GYRO_INT J1 137 DI Gyroscopic sensor interrupt ACCEL_INT J1 139 DI Acceleration sensor interrupt ADC Interfaces Pin Name Pin No I O Description DC Characteristics Comment ADC_PMU_GPIO8 J2 153 AI General pu...
Страница 32: ...a 47 kΩ resistor BAT_P J2 163 AI Battery voltage detect Must be connected BAT_M J2 165 AI Battery voltage detect CS_P J2 157 AI Current sense CS_M J2 159 AI Current sense BAT_RBIAS J3 11 PO Power supply for NTC pull up circuit If NTC 10 kΩ pull BAT_THERM up to BAT_RBIAS with a 12 kΩ resistor If NTC 47 kΩ keep BAT_RBIAS open BAT_ID J3 16 AI Battery type detect SMB_USB_IN J3 2 J3 3 J3 4 J3 5 J3 6 J3...
Страница 33: ...t CODEC_RST J2 90 DO Codec reset VOLmax 0 45 V VOHmin 1 35 V 1 8 V power domain CODEC_INT1 J2 91 DI Codec interrupt 1 VILmax 0 63 V VIHmin 1 17 V CODEC_INT2 J2 93 DI Codec interrupt 2 CODEC_SPI_CS J2 96 DO SPI chip select for codec VOLmax 0 45 V VOHmin 1 35 V CODEC_SPI_CLK J2 92 DO SPI clock for codec CODEC_SPI_MOSI J2 94 DO SPI master out slave in for codec CODEC_SPI_MISO J2 89 DI SPI master in s...
Страница 34: ...V I2S2_DATA1 J2 61 DIO I2S2 data channel 1 I2S3_WS J2 63 DO I2S3 word select VOLmax 0 45 V VOHmin 1 35 V I2S3_SCK J2 73 DO I2S3 bit clock I2S3_DATA0 J2 69 DIO I2S3 data channel 0 VILmax 0 63 V VIHmin 1 17 V VOLmax 0 45 V VOHmin 1 35 V I2S3_DATA1 J2 65 DIO I2S3 data channel 1 I2S3_DATA2 J2 67 DIO I2S3 data channel 2 I2S3_DATA3 J2 71 DIO I2S3 data channel 3 GPIO Interfaces Pin Name Pin No I O Descri...
Страница 35: ... SPI2_CLK J2 52 DO SPI2 clock VOLmax 0 45 V VOHmin 1 35 V 1 8 V power domain SPI2_CS J2 54 DO SPI2 chip select SPI2_MOSI J2 58 DO SPI2 master out slave in SPI2_MISO J2 56 DI SPI2 master in salve out VILmax 0 63 V VIHmin 1 17 V SPI0_CLK J2 86 DO SPI0 clock VOLmax 0 45 V VOHmin 1 35 V SPI0_CS J2 80 DO SPI0 chip select SPI0_MOSI J2 82 DO SPI0 master out slave in SPI0_MISO J2 84 DI SPI0 master in salv...
Страница 36: ...1 DO DisplayPort auxiliary channel switch output enable VOLmax 0 45 V VOHmin 1 35 V 1 8 V power domain SBU_SW_SEL J2 3 DO DisplayPort auxiliary channel switch select Vibrator Drive Interface Pin Name Pin No I O Description DC Characteristics Comment HAP_PWM_IN J3 18 DI Haptic PWM input HAP_P J3 20 AO Haptic driver output HAP_M J3 19 AO Haptic driver output UFS Interface Pin Name Pin No I O Descrip...
Страница 37: ...rch modes FLASH_LED2 J4 20 J4 21 AO Flash torch driver output 2 ILED2 1 5 A FLASH_LED3 J4 5 J4 6 AO Flash torch driver output 3 ILED3 0 75 A VRTC Interface Pin Name Pin No I O Description DC Characteristics Comment VRTC J2 133 PI P O Power supply for RTC Vnom 3 2 V VI 2 5 3 2 V Emergency Download Interface Pin Name Pin No I O Description DC Characteristics Comment USB_BOOT J2 130 DI Forces the mod...
Страница 38: ...ables CBL_PWR_N J1 134 DI Initiates power on when grounded DBG_TXD J2 137 DO Debug UART transmit VOLmax 0 45 V VOHmin 1 35 V 1 8 V power domain DBG_RXD J2 135 DI Debug UART receive VILmax 0 63 V VIHmin 1 17 V PMU_GPIO10 J2 147 DIO General purpose input output VILmax 0 63 V VIHmin 1 17 V VOLmax 0 45 V VOHmin 1 35 V PMU_GPIO13 J2 149 DIO General purpose input output Reserved Pins Pin Name Pin No Com...
Страница 39: ...s below 3 1 V the module will be powered off automatically Therefore make sure the input voltage will never drop below 3 1 V 3 1 V Voltage 3 8 V Input current 3 A Figure 3 Voltage Drop Sample To decrease voltage drop a bypass capacitor of about 100 µF with low ESR ESR 0 7 Ω should be used for the VBAT inputs and a multi layer ceramic chip capacitor MLCC array should also be used due to its ultra l...
Страница 40: ...is not used it is recommended to use a regulator for the module If the voltage difference between the input and output is not too high it is suggested to use an LDO to supply power for the module If there is a big voltage difference between the input source and the desired output VBAT a buck converter is preferred to be used as the power supply The following figure shows a reference design for 12 ...
Страница 41: ...y between the output of the inductor L1 and the VBAT pins of the module 3 When the battery voltage is below 3 1 V the system will trigger automatic shutdown so the design of power supply should be consistent with the configuration of fuel gauge driver 3 5 Turn on and off Scenarios 3 5 1 Turn on the Module Using PWRKEY The module can be turned on by driving PWRKEY low for at least 1 6 s PWRKEY is p...
Страница 42: ...ESD protection A reference circuit is shown in the following figure PWRKEY S1 Close to S1 TVS 1K Figure 7 Turn on the Module Using Keystroke The timing of turning on is illustrated in the following figure VBAT Typ 3 8 V PWRKEY 1 6 s Others VREG_S4A_1V8 30 s SD_LDO13A 40 7 ms Software controlled LDO24A_3V075 Active LDO12A_1V8 Note2 Software controlled Figure 8 Timing of Turning on the Module ...
Страница 43: ...PWRKEY Additionally PWRKEY cannot be pulled down all the time 3 5 2 Turn on the Module Automatically Using CBL_PWR_N The module can be turned on automatically by driving the CBL_PWR_N pin to GND through a 1 kΩ resistor CBL_PWR_N pin is pulled up internally A simple reference circuit is illustrated in the following figure CBL_PWR_N Module 1K Figure 9 Turn on the Module Using CBL_PWR_N The module ca...
Страница 44: ...illustrated in the following figure VBAT PWRKEY Others 8 s Restart Figure 10 Timing of Restarting the Module 3 6 VRTC Interface The RTC Real Time Clock can be powered by an external power source through VRTC when the module is powered down and there is no power supply for the VBAT The external power source can be a rechargeable battery such as coin cell according to application demands The followi...
Страница 45: ...y should be less than 2 kΩ and it is recommended to use the MS621FE FL11E of SEIKO 3 7 Power Output SA800U WF supports output of regulated voltages for peripheral circuits During application it is recommended to use parallel capacitors 33 pF and 10 pF in the circuit to suppress high frequency noise Table 5 Power Description Pin Name Default Voltage V Drive Current mA Comment VREG_S4A_1V8 1 8 2000 ...
Страница 46: ...en the battery voltage is between the maximum pre charge voltage and 4 35 V 3 0 4 35 V programmable 4 35 V by default the system will switch to CC mode The charging current is programmable from 300 4500 mA The default charging current is 500 mA for USB charging and 4000 mA for adapter Constant voltage mode CV mode When the battery voltage reaches the final value 4 35 V the system will switch to CV...
Страница 47: ...Must be connected BAT_M J2 165 AI Battery voltage detect CS_P J2 157 AI Current sense CS_M J2 159 AI Current sense BAT_RBIAS J3 11 PO Power supply for NTC pull up circuit If NTC 10 kΩ pull BAT_THERM up to BAT_RBIAS with a 12 kΩ resistor If NTC 47 kΩ keep BAT_RBIAS open BAT_ID J3 16 AI Battery type detect SMB_USB_IN J3 2 J3 3 J3 4 J3 5 J3 6 J3 7 PO Power output for SMB1355 parallel charging Paralle...
Страница 48: ...s you to estimate the battery life based on the battery level to timely save important data before complete power down Mobile devices such as mobile phone and game machine systems are powered by batteries When different batteries are used the charging and discharging curve has to be modified according to the battery type to achieve the best performance If thermistor is not available in the battery...
Страница 49: ...ugh USB_SS1 when it is plugged in with the other side up USB_CC2 will detect the external device and the data will be transmitted through USB_SS2 The following table shows the pin definition of USB Type C interface The following table shows the pin definition of USB1 interface Table 7 Pin Definition of USB TYPE C Interface Pin Name Pin No I O Description Comment USB_VBUS J2 160 J2 162 J2 164 J2 16...
Страница 50: ...WF can support E mark cable and active cable Table 8 Pin Definition of VCONN Circuit USB1_SS2_TX_M J2 111 AO USB1 3 1 channel 2 super speed transmit USB1_SS2_TX_P J2 113 AO USB1 3 1 channel 2 super speed transmit USB1_SS2_RX_M J2 114 AI USB1 3 1 channel 2 super speed receive USB1_SS2_RX_P J2 112 AI USB1 3 1 channel 2 super speed receive USB_CC1 J2 141 AI USB Type C configuration channel 1 USB_CC2 ...
Страница 51: ...ort mode with 4 lanes up to 4K 60 fps over USB Type C The pin definition of USB Type C DisplayPort mode is listed below Table 9 Pin Definition of USB Type C DisplayPort Mode Pin Name USB Type C Mode DisplayPort Mode USB1_SS2_RX_P M USB1_SS2_RX_P M DP_LANE0_P M USB1_SS2_TX_P M USB1_SS2_TX_P M DP_LANE1_P M USB1_SS1_RX_P M USB1_SS1_RX_P M DP_LANE3_P M USB1_SS1_TX_P M USB1_SS1_TX_P M DP_LANE2_P M EDP_...
Страница 52: ...V8 0 1 μF 0 1 μF Module 1 μF SBU1 SBU2 2 2K SGM7227YMS10G TR SBU_SW_SEL C3 C4 C5 C6 C1 C2 R1 R1 R3 C3 Figure 15 DisplayPort Reference Design 3 9 2 USB2 Interface USB2 only supports host mode The following table shows the pin definition of USB2 interface Table 10 Pin Definition of USB2 Pin Name Pin No I O Description Comment USB2_DP J2 105 AIO USB2 2 0 differential data 90 Ω differential impedance ...
Страница 53: ...erence Design USB2 for Host Mode 3 9 3 Design Principles Table 11 USB Trace Length Inside the Module USB2_SS_RX_M J2 100 AI USB2 3 1 channel 1 super speed receive USB2_SS_RX_P J2 102 AI USB2 3 1 channel 1 super speed receive Pin No Signal Length mm Length Difference P M J2 117 USB1_DM 39 59 0 15 J2 119 USB1_DP 39 44 J2 123 USB1_SS1_TX_M 22 37 0 90 J2 125 USB1_SS1_TX_P 23 27 J2 118 USB1_SS1_RX_M 19...
Страница 54: ...ides Do not route USB 3 1 signal lines under RF signal lines Crossing or parallel with RF signal lines is forbidden Isolation between USB 3 1 signals and RF signals should be more than 90 dB Otherwise the RF signals will be seriously affected Keep the ESD protection devices as close as possible to the USB connector Make sure the intra pair length difference within USB 2 0 differential pair and tha...
Страница 55: ...ND B1 B2 VREG_S4A_1V8 DBG_RXD DBG_TXD RXD _3 3V TXD _3 3V VDD _3 3V TXS0102DCUR C1 100 pF C2 U1 100 pF Figure 17 Reference Circuit with Level Translator Chip The following figure is an example of connection between SA800U WF and PC A level translator and an RS 232 level translator chip is recommended to be added between the module and PC as shown below TXS0102DCUR RXD _3 3V VCCA Module GND GND 1 8...
Страница 56: ...CIE0_REFCLK_P J1 15 AO PCIe0 reference clock Control the characteristic impedance as 85 Ω PCIE0_REFCLK_M J1 17 AO PCIe0 reference clock PCIE0_TX_P J1 11 AO PCIe0 transmit PCIE0_TX_M J1 9 AO PCIe0 transmit PCIE0_RX_P J1 21 AI PCIe0 receive PCIE0_RX_M J1 23 AI PCIe0 receive PCIE1_RST_N J1 107 DO PCIe1 reset PCIE1_WAKE_N J1 111 DI PCIe1 wakes up host PCIE1_CLKREQ_N J1 109 DI PCIe1 clock request PCIE1...
Страница 57: ...Circuit To enhance the reliability and availability in applications follow the criteria below in the circuit design of PCIe interfaces Keep the PCIe signals away from noisy signals such as clock signals SMPS and so forth It is recommended to place the AC coupling capacitors C1 C2 C3 C4 close to the TX side to ensure signal integrity of trace routing on PCB Keep the intra pair length difference wit...
Страница 58: ... SD_LDO13A J4 11 PO 1 8 2 95 V output power for SD card pull up circuits Vnom 1 8 2 95 V IOmax 50 mA SD_CLK J1 45 DO SD card clock Control characteristic impedance as 45 Ω SD_CMD J1 47 DO SD card command SD_DATA0 J1 51 DIO SDIO data bit 0 SD_DATA1 J1 53 DIO SDIO data bit 1 SD_DATA2 J1 57 DIO SDIO data bit 2 SD_DATA3 J1 55 DIO SDIO data bit 3 SD_DET J1 49 DI SD card hot plug detect Active low SDC4_...
Страница 59: ...ive power a 4 7 μF and a 33 pF capacitor should be added in parallel near the SD card connector SD_CMD SD_CLK SD_DATA0 SD_DATA1 SD_DATA2 and SD_DATA3 are all high speed signal lines In PCB design control the characteristic impedance of them to 45 Ω and do not cross them with other traces It is recommended to route these traces on the inner layer of PCB and keep them of the same trace length Additi...
Страница 60: ...D_DATA3 14 10 Pin Name Pin No I O Description Comment GPIO_25 J2 2 DIO General purpose input output GPIO_42 J2 64 DIO General purpose input output GPIO_44 J2 66 DIO General purpose input output Wakeup 1 GPIO_49 J2 78 DIO General purpose input output Wakeup GPIO_50 J2 70 DIO General purpose input output GPIO_52 J2 68 DIO General purpose input output Wakeup GPIO_122 J2 74 DIO General purpose input o...
Страница 61: ... dedicated to support low power and always on use cases Table 17 Pin Definition of I2C Interfaces GPIO_135 J2 134 DIO General purpose input output Pin Name Pin No I O Description Comment TP_I2C_SCL J2 44 OD TP I2C clock Used for touch panel TP_I2C_SDA J2 46 OD TP I2C data I2C4_SDA J2 4 OD I2C4 data I2C4_SCL J2 6 OD I2C4 clock I2C10_SCL J2 75 OD I2C10 clock I2C10_SDA J2 77 OD I2C10 data CCI0_I2C_SC...
Страница 62: ...2 DO SPI2 clock 1 8 V power domain SPI2_CS J2 54 DO SPI2 chip select SPI2_MISO J2 56 DI SPI2 master in salve out SPI2_MOSI J2 58 DO SPI2 master out slave in SPI0_CLK J2 86 DO SPI0 clock SPI0_CS J2 80 DO SPI0 chip select SPI0_MISO J2 84 DI SPI0 master in salve out SPI0_MOSI J2 82 DO SPI0 master out slave in SPI11_CLK J2 99 DO SPI11 clock SPI11_CS J2 101 DO SPI11 chip select SPI11_MISO J2 97 DI SPI1...
Страница 63: ...ive Interface SA800U WF supports eccentric rotating mass ERM motor and linear resonant actuator LRA The pin definition of vibrator drive interface is listed below Table 20 Pin Definition of Vibrator Drive Interface Pin Name Pin No I O Description Comment ADC_PMU_GPIO8 J2 153 AI General purpose ADC interface Maximum input voltage 1 8 V ADC_PMU_GPIO21 J2 151 AI General purpose ADC interface Maximum ...
Страница 64: ...s 8 lanes can support QUXGA display resolution 3840 2160 The module supports dual LCD independent display default DSI DP over USB Type C optional DSI0 DSI1 Please note that DSI1 does not support screens with command mode Table 21 Pin Definition of LCM Interfaces Pin Name Pin No I O Description Comment LDO14A_1V88 J4 9 PO 1 8 V output for IOVDD of LCDs Vnom 1 8 V IOmax 50 mA LCD_RST J2 62 DO LCD re...
Страница 65: ...J2 37 AO LCD1 MIPI lane 1 data DSI1_LN1_P J2 39 AO LCD10 MIPI lane 1 data DSI1_LN2_N J2 27 AO LCD1 MIPI lane 2 data DSI1_LN2_P J2 25 AO LCD1 MIPI lane 2 data DSI1_LN3_N J2 31 AO LCD1 MIPI lane 3 data DSI1_LN3_P J2 33 AO LCD1 MIPI lane 3 data LCD_BL_A J4 4 PO Power output for LCD backlight LCD_BL_K1 J4 3 AI Current sink 1 for LCD backlight LCD_BL_K2 J4 2 AI Current sink 2 for LCD backlight LCD_BL_K...
Страница 66: ...TDN3 GND MIPI_TDP2 MIPI_TDN2 GND MIPI_TDP1 MIPI_TDN1 GND LCD_BL_A LCD_BL_K1 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 MIPI_TDP0 MIPI_TDN0 GND MIPI_TCP MIPI_TCN 29 28 30 3 4 5 6 3 4 5 6 3 4 5 6 3 4 5 6 DSI0_LN1_N DSI0_LN1_P DSI0_LN0_N DSI0_LN0_P 1 2 3 4 5 6 11 1 2 1 2 1 2 1 2 100 nF 4 7 μF 1 μF Module LCM FL1 FL2 FL3 FL4 FL5 EMI filter C3 C2 C1 NC GND GND GND GND 31 32 33...
Страница 67: ... 2 μF R1 Figure 23 Reference Circuit Design for LCM1 Interface MIPI are high speed signals It is recommended that common mode filters should be added in series near the LCM connector so as to improve protection against electromagnetic radiation interference ICMEF112P900MFR is recommended When compatible design with other displays is required connect the LCD_ID pin of LCM to the module s ADC pin an...
Страница 68: ...M_PMI_GPIO5 Module 2 2 μF Backlight Driver LCM1_LED VBAT C1 R1 10K Figure 24 Reference Design of LCM1 External Backlight Driving Circuit 3 19 Touch Panel Interface SA800U WF provides one I2C interface to connect with touch panel and also provides the corresponding power supply and interrupt pins The pin definition of touch panel interfaces is illustrated below Table 22 Pin Definition of Touch Pane...
Страница 69: ...MP The 2 lane MIPI CSI can only receive data of RAW format It can be used for ToF 3D camera modules and cannot be used for display The video and photo quality are determined by various factors such as camera sensor camera lens quality etc Table 23 Pin Definition of Camera Interfaces Pin Name Pin No I O Description Comment LVS1A_1V8 J1 149 PO 1 8 V output for IOVDD of cameras Vnom 1 8 V IOmax 300 m...
Страница 70: ...f camera 1 CSI1_LN2_N J1 42 AI MIPI lane 2 data of camera 1 CSI1_LN2_P J1 40 AI MIPI lane 2 data of camera 1 CSI1_LN3_N J1 34 AI MIPI lane 3 data of camera 1 CSI1_LN3_P J1 36 AI MIPI lane 3 data of camera 1 CSI2_CLK_N J1 63 AI MIPI clock of camera 2 CSI2_CLK_P J1 61 AI MIPI clock of camera 2 CSI2_LN0_N J1 67 AI MIPI lane 0 data of camera 2 CSI2_LN0_P J1 69 AI MIPI lane 0 data of camera 2 CSI2_LN1_...
Страница 71: ...1 118 DO Strobe of camera 2 CAM0_MCLK J1 91 DO Master clock of camera 0 CAM1_MCLK J1 95 DO Master clock of camera 1 CAM2_MCLK J1 99 DO Master clock of camera 2 CAM3_MCLK J1 103 DO Master clock of camera 3 CAM0_RST J1 100 DO Reset of camera 0 CAM1_RST J1 96 DO Reset of camera 1 CAM2_RST J1 124 DO Reset of camera 2 CAM3_RST J1 126 DO Reset of camera 3 CAM0_PWDN J1 114 DO Power down of camera 0 CAM1_...
Страница 72: ...I0_ LN0_N CSI0_ LN1_P CSI0_ LN1_N CSI0_ LN2_P CSI0_ LN2_N CSI0_ LN3_P CSI0_ LN3_N CAM0_AVDD CAM0_AF_VDD CAM0_DVDD LVS1A_1V8 AFVDD MODULE CAM0_STROBE 1 μF 4 7 μF 4 7 μF R1 R2 C1 C2 C3 C4 Figure 26 Reference Circuit Design for CSI0 CAM1_DVDD_EN J1 130 DO DVDD enable of camera 1 CAM2_DVDD_EN J1 110 DO DVDD enable of camera 2 CAM3_DVDD_EN J1 128 DO DVDD enable of camera 3 CCI0_I2C_SCL J1 142 OD CCI0 I...
Страница 73: ...N R1 100K C2 CAM0_DVDD Module 2 2 μF DCDC_IC VBAT C5 CAM0_DVDD_EN R3 100K C6 CAM0_AVDD Module 2 2 μF LDO_IC VBAT C3 R2 100K C4 CAM0_AVDD_EN L1 2 2 μF 2 2 μF 2 2 μF Figure 27 Reference Circuit Design for Power of CSI0 CSI3 can only receive data of RAW format It can be used for ToF 3D camera modules but cannot be used for display NOTE ...
Страница 74: ...ls keep all the MIPI traces of the same length Route the CAM_MCLK signals in the inner layer of the PCB and surround them with ground Spacing for the lanes should comply with the following rules a Intra lane P to N 1 trace width b Lane to lane 1 5 trace width c Lanes to all other signals 2 5 trace width Route MIPI traces according to the following rules a Control the differential impedance to 100 ...
Страница 75: ...t is listed above 3 The maximum PCB trace length listed above includes the length routed inside the module Table 26 MIPI Trace Length Inside the Module Data Rate Flex Cable Length inch Cable Insertion Loss dB Maximum PCB Trace Length mm 500 Mbps lane 3 0 8 280 6 1 4 210 750 Mbps lane 3 1 210 6 1 5 150 1 0 Gbps lane 3 1 1 200 6 1 7 100 1 5 Gbps lane 3 1 2 135 6 2 2 40 2 1 Gbps lane 3 1 6 110 6 2 8 ...
Страница 76: ...29 J2 15 DSI1_LN0_P 22 71 J2 37 DSI1_LN1_N 23 35 0 67 J2 39 DSI1_LN1_P 24 02 J2 27 DSI1_LN2_N 22 45 0 54 J2 25 DSI1_LN2_P 22 99 J2 31 DSI1_LN3_N 23 73 0 46 J2 33 DSI1_LN3_P 23 27 J1 30 CSI0_CLK_N 23 90 0 36 J1 28 CSI0_CLK_P 23 54 J1 22 CSI0_LN0_N 24 31 0 12 J1 24 CSI0_LN0_P 24 19 J1 16 CSI0_LN1_N 23 33 0 34 J1 18 CSI0_LN1_P 22 99 J1 10 CSI0_LN2_N 24 53 0 42 J1 12 CSI0_LN2_P 24 95 J1 6 CSI0_LN3_N 2...
Страница 77: ...J1 34 CSI1_LN3_N 15 61 0 30 J1 36 CSI1_LN3_P 15 31 J1 63 CSI2_CLK_N 16 36 0 36 J1 61 CSI2_CLK_P 16 72 J1 67 CSI2_LN0_N 15 84 0 25 J1 69 CSI2_LN0_P 16 09 J1 66 CSI2_LN1_N 15 71 0 40 J1 64 CSI2_LN1_P 16 11 J1 72 CSI2_LN2_N 14 90 0 49 J1 70 CSI2_LN2_P 15 39 J1 78 CSI2_LN3_N 15 98 0 49 J1 76 CSI2_LN3_P 16 47 J1 85 CSI3_CLK_N 10 27 0 08 J1 87 CSI3_CLK_P 10 35 J1 81 CSI3_LN0_N 9 57 0 11 J1 79 CSI3_LN0_P...
Страница 78: ...00 mA for each whether the two LEDs work together or separately As for FLASH_LED3 in flash mode the maximum output current is 0 75 A and in torch mode the maximum output current is 500 mA Table 27 Pin Definition of Flashlight Interfaces A reference circuit design is shown below Module D2 FLASH_LED1 D1 FLASH_LED2 D3 FLASH_LED3 Figure 28 Reference Circuit Design for Flashlight Interfaces Pin Name Pi...
Страница 79: ...on Comment SSC_SPI1_CS0 J1 136 DO Sensor core SPI1 chip select 0 1 8 V power domain SSC_SPI1_CS1 J1 138 DO Sensor core SPI1 chip select 1 SSC_SPI1_CS2 J1 140 DO Sensor core SPI1 chip select 2 SSC_SPI1_CLK J1 154 DO Sensor core SPI1 clock SSC_SPI1_MOSI J1 152 DO Sensor core SPI1 master out slave in SSC_SPI1_MISO J1 150 DI Sensor core SPI1 master in salve out SSC_SPI2_CS J1 141 DO Sensor core SPI2 c...
Страница 80: ...DEC_SPI_CLK J2 92 DO SPI clock for codec CODEC_SPI_MOSI J2 94 DO SPI master out slave in for codec CODEC_SPI_CS J2 96 DO SPI chip select for codec CODEC_SPI_MISO J2 89 DI SPI master in salve out for codec CODEC_INT1 J2 91 DI Codec interrupt 1 CODEC_INT2 J2 93 DI Codec interrupt 2 WCD_CLK J2 43 DO WCD clock SLIMBUS_CLK J2 51 DO SLIMbus clock SLIMBUS_DATA0 J2 47 DIO SLIMbus data bit 0 SLIMBUS_DATA1 ...
Страница 81: ...al startup or operation For convenient firmware upgrade and debugging in the future please reserve the reference circuit design shown as below VREG_S4A_1V8 S1 Module USB_BOOT R1 10K Figure 29 Reference Circuit Design for Emergency Download Interface I2S2_DATA1 J2 61 DIO I2S2 data channel 1 I2S3_WS J2 63 DO I2S3 word select I2S3_DATA1 J2 65 DIO I2S3 data channel 1 I2S3_DATA2 J2 67 DIO I2S3 data cha...
Страница 82: ...ramic antenna can be connected to the module via these connectors so as to achieve Wi Fi and BT functions means under development 4 1 Wi Fi Overview SA800U WF supports 2 4 GHz and 5 GHz dual band WLAN wireless communication based on IEEE 802 11a b g n ac standard protocols The maximum data rate is up to 866 Mbps The features are as below Support 2 2 MIMO Support Wake on WLAN WoWLAN Support ad hoc ...
Страница 83: ...dB 802 11g 54 Mbps 14 dBm 2 5 dB 802 11n HT20 MCS0 16 dBm 2 5 dB 802 11n HT20 MCS7 13 dBm 2 5 dB 802 11n HT40 MCS0 16 dBm 2 5 dB 802 11n HT40 MCS7 13 dBm 2 5 dB 5 GHz 802 11a 6 Mbps 17 dBm 2 5 dB 802 11a 54 Mbps 15 dBm 2 5 dB 802 11n HT20 MCS0 16 dBm 2 5 dB 802 11n HT20 MCS7 14 dBm 2 5 dB 802 11n HT40 MCS0 16 dBm 2 5 dB 802 11n HT40 MCS7 14 dBm 2 5 dB 802 11ac VHT20 MCS0 16 dBm 2 5 dB 802 11ac VHT...
Страница 84: ...bps 96 dBm 802 11b 11 Mbps 87 dBm 802 11g 6 Mbps 90 dBm 802 11g 54 Mbps 74 dBm 802 11n HT20 MCS0 90 dBm 802 11n HT20 MCS7 72 dBm 802 11n HT40 MCS0 87 dBm 802 11n HT40 MCS7 70 dBm 5 GHz 802 11a 6 Mbps 91 dBm 802 11a 54 Mbps 75 dBm 802 11n HT20 MCS0 91 dBm 802 11n HT20 MCS7 72 dBm 802 11n HT40 MCS0 87 dBm 802 11n HT40 MCS7 70 dBm 802 11ac VHT20 MCS8 68 dBm 802 11ac VHT40 MCS9 64 dBm 802 11ac VHT80 M...
Страница 85: ...ccommodate 79 channels The BLE channel bandwidth is 2 MHz and can accommodate 40 channels Table 32 BT Data Rate and Versions Reference specifications are listed below Bluetooth Radio Frequency TSS and TP Specification 1 2 2 0 2 0 EDR 2 1 2 1 EDR 3 0 3 0 HS August 6 2009 Bluetooth Low Energy RF PHY Test Specification RF PHY TS 4 0 0 December 15 2009 Bluetooth 5 0 RF PHY Cover Standard RF PHY TS 5 0...
Страница 86: ...s the BT transmitting and receiving performance of SA800U WF module Table 33 BT Transmitting and Receiving Performance Transmitter Performance Packet Types DH5 2 DH5 3 DH5 Transmitting Power 7 5 dBm 2 5 dB 7 5 dBm 2 5 dB 8 dBm 2 5 dB Receiver Performance Packet Types DH5 2 DH5 3 DH5 Receiving Sensitivity 92 dBm 93 dBm 86 dBm ...
Страница 87: ...ctor ANT CH1 Wi Fi MIMO antenna connector BT BT antenna connector and FM FM antenna connector respectively The impedance of the antenna connectors is 50 Ω Figure 30 Antenna Connectors Table 34 Definition of Antenna Connectors Antenna Connector Name I O Description Comment ANT CH0 AIO Wi Fi BT antenna connector 50 Ω impedance ANT CH1 AIO Wi Fi MIMO antenna connector 50 Ω impedance FM BT ANT CH0 ANT...
Страница 88: ...s the requirements for Wi Fi BT FM antennas Table 36 Antenna Requirements BT AIO BT antenna connector 50 Ω impedance FM AI FM antenna connector 50 Ω impedance Type Frequency Unit 802 11a b g n ac 2402 2482 5180 5825 MHz BT 5 0 2402 2480 MHz FM 76 108 MHz Antenna Type Requirements Wi Fi BT FM VSWR 2 Gain 1 dBi Max Input Power 50 W Input Impedance 50 Ω Polarization Type Vertical Cable Insertion Loss...
Страница 89: ... 2 2 Recommended Mating Plug for Antenna Connection SA800U WF is mounted with RF connectors receptacles for convenient antenna connection The connector being used is 818000500 from ECT and its dimensions are shown as below Figure 31 Dimensions of the ECT 818000500 Connector Unit mm ...
Страница 90: ... Module Series SA800U WF Hardware Design SA800U WF_Hardware_Design 89 106 The mating plug listed in the following figure can be used to match the receptacles Figure 32 Mechanicals of the Mating Plug Unit mm ...
Страница 91: ...solute Maximum Ratings 6 2 Power Supply Ratings Table 38 SA800U WF Power Supply Ratings Parameter Min Max Unit VBAT 0 3 6 V USB_VBUS 0 3 28 V Voltage on Digital Pins 0 5 2 3 V Parameter Description Conditions Min Typ Max Unit VBAT VBAT The actual input voltages must fall between the minimum and maximum values 3 55 3 8 4 4 V Voltage drop during power on Maximum power control level during power on 4...
Страница 92: ...nsumption The current consumption of different conditions is listed in the following table Table 40 SA800U WF Current Consumption 2 2 MIMO USB_VBUS Charging power input Power output for OTG device USB charger insertion detection 4 0 5 0 14 V VRTC Power supply voltage of backup battery 2 5 3 2 3 2 V Parameter Min Typ Max Unit Operating temperature range 1 35 25 75 C Storage temperature range 40 90 ...
Страница 93: ...Hz 770 mA 300 Mbps 40 MHz 615 mA Wi Fi 802 11ac Tx 14 4 Mbps 20 MHz 760 mA 173 2 Mbps 20 MHz 655 mA 30 Mbps 40 MHz 740 mA 400 Mbps 40 MHz 610 mA 65 Mbps 80 MHz 685 mA 866 6 Mbps 80 MHz 565 mA Wi Fi 802 11a Rx 54 Mbps 160 mA Wi Fi 802 11b Rx 11 Mbps 175 mA Wi Fi 802 11g Rx 54 Mbps 155 mA Wi Fi 802 11n Rx 300 Mbps 40 MHz 615 mA Wi Fi 802 11ac Rx 866 6 Mbps 80 MHz 550 mA BT Tx Channel 0 110 mA BT Tx ...
Страница 94: ...ditions such as with maximum power for a long time it is strongly recommended to apply thermal conductive gap fillers to the gaps between the shielding cover and heat generating components in the module for better thermal dissipation There are other measures to enhance thermal dissipation Place the module away from other heat sources Select a suitable mechanical enclosure for the terminal product ...
Страница 95: ...llowing figure shows the thermal dissipation area Figure 33 Thermal Dissipation If a conformal coating is necessary for the module do NOT use any coating material that may chemically react with the PCB or shielding cover and prevent the coating material from flowing into the module NOTE ...
Страница 96: ...7 Mechanical Dimensions This chapter describes the mechanical dimensions of the module All dimensions are measured in millimeter mm and the dimension tolerances are 0 05 mm unless otherwise specified 7 1 Mechanical Dimensions of the Module Figure 34 Module Top and Side Dimensions ...
Страница 97: ...Smart Module Series SA800U WF Hardware Design SA800U WF_Hardware_Design 96 106 Figure 35 Module Bottom Dimensions Bottom View ...
Страница 98: ...ecommended Footprint Top View 1 For easy maintenance of the module keep about 5 mm between the module and other components on the host PCB 2 All RESERVED pins should be kept open and MUST NOT be connected to ground 3 The 168 pin connector FX10A 168S SV 21 of HIROSE should be used for connection with the module NOTES ...
Страница 99: ...p and Bottom View of the Module Figure 37 Top View of SA800U WF Module Figure 38 Bottom View of SA800U WF Module Images above are for illustration purpose only and may differ from the actual module For authentic appearance and label please refer to the module received from Quectel NOTE ...
Страница 100: ...ould be 35 60 2 The storage life in vacuum sealed packaging is 12 months in Recommended Storage Condition 3 The floor life of the module is 168 hours 1 in a plant where the temperature is 23 5 C and relative humidity is below 60 After the vacuum sealed packaging is removed the module must be installed within 168 hours Otherwise the module should be stored in an environment where the relative humid...
Страница 101: ...Design SA800U WF_Hardware_Design 100 106 8 2 Packaging SA800U WF is packaged in tray carriers Each tray is 350 mm 245 mm 15 8 mm and contains 18 modules The following figures show the package details measured in mm Figure 39 Tray Dimensions ...
Страница 102: ...0U WF_Hardware_Design 101 106 10 trays are overlaid in one vacuum sealed package The package details are shown below Figure 40 Package Details Table 42 Tray Package Model Name MOQ for MP Minimum Package 180 pcs SA800U WF 180 pcs N W 4 67 kg G W 5 07 kg ...
Страница 103: ...r SA800U WF 2 Quectel_SA800U WF_Pin_Description_and_GPIO_ Configuration Pin Description and GPIO Configuration of SA800U WF 3 Quectel_SA800U WF_Reference_Design Reference Design for SA800U WF Abbreviation Description 3D 3 Dimensional ADC Analog to Digital Converter AP Access Point B2B Board to Board BOB Buck or Boost bps Bits per Second BT Bluetooth CS Coding Scheme CSI Camera Serial Interface CTS...
Страница 104: ...trostatic Discharge ESR Equivalent Series Resistance EVRC Enhanced Variable Rate Codec EVS Enhanced Voice Services FM Frequency Modulation GPIO General Purpose Input Output GPU Graphics Processing Unit HK ADC Housekeeping ADC HT High Throughput I2C Inter Integrated Circuit I2S Inter IC Sound IEEE Institute of Electrical and Electronics Engineers Imax Maximum Load Current I O Input Output ISP Image...
Страница 105: ...er Ceramic Capacitor NTC Negative Temperature Coefficient OTG On The Go OVP Over Voltage Protection PCB Printed Circuit Board PCIe Peripheral Component Interconnect Express PHY Physical Layer PMU Power Management Unit PWM Pulse Width Modulation QC Quick Charge QCELP Qualcomm Code Excited Linear Prediction QUXGA Quad Ultra Extended Graphics Array RF Radio Frequency RFFE RF Front End RoHS Restrictio...
Страница 106: ...niversal Asynchronous Receiver Transmitter UFS Universal Flash Storage USB Universal Serial Bus VESA Video Electronics Standards Association VHT Very High Throughput Vmax Maximum Voltage Value Vnom Nominal Voltage Value Vmin Minimum Voltage Value VI Voltage Input VIHmax Maximum Input High Level Voltage Value VIHmin Minimum Input High Level Voltage Value VILmax Maximum Input Low Level Voltage Value...
Страница 107: ...m Output High Level Voltage Value VOHmin Minimum Output High Level Voltage Value VOLmax Maximum Output Low Level Voltage Value VOLmin Minimum Output Low Level Voltage Value WAPI WLAN Authentication and Privacy Infrastructure WLAN Wireless Local Area Network WLED White LED XO Crystal Oscillator ...
