M50 Hardware Design
M50_HD_V2.0
- 63 -
3.13.2. Timing
The sample rate of the PCM interface is 8 KHz and the clock source is 256 KHz, so every frame
contains 32 bits data, since M50 supports 16 bits line code PCM format, the left 16 bits are invalid.
The following diagram shows the timing of different combinations. The synchronization length in
long synchronization format can be programmed by firmware from one bit to eight bits. In the
Sign extension mode, the high three bits of 16 bits are sign extension, and in the Zero padding
mode, the low three bits of 16 bits are zero padding.
12 11 10
9
8
7
6
5
4
3
2
1
0
12 11 10
9
8
7
6
5
4
3
2
1
0
PCM_CLK
PCM_SYNC
PCM_OUT
PCM_IN
MSB
MSB
Sign extension
Sign extension
Figure 38: Long synchronization & Sign extension diagram
12 11 10
9
8
7
6
5
4
3
2
1
0
12 11 10
9
8
7
6
5
4
3
2
1
0
PCM_CLK
PCM_SYNC
PCM_OUT
PCM_IN
MSB
MSB
Zero padding
Zero padding
Figure 39: Long synchronization & Zero padding diagram
PCM_CLK
PCM_SYNC
PCM_OUT
PCM_IN
12 11 10
9
8
7
6
5
4
3
2
1
0
12 11 10
9
8
7
6
5
4
3
2
1
0
MSB
MSB
Sign extension
Sign extension
Figure 40: Short synchronization & Sign extension diagram
Quecctel
Confidential
