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LTE-A Module Series
EG18 Hardware Design
EG18_Hardware_Design 56 / 104
PCM_CLK
PCM_SYNC
PCM_OUT
MSB
LSB
PCM_IN
125
μ
s
MSB
1
2
32
31
LSB
Figure 28: Auxiliary Mode Timing
The following table shows the pin definition of PCM interface and I2C interface, both of which can be
applied on audio codec design.
Table 18: Pin Definition of PCM interface and I2C Interface
Pin Name
Pin No.
I/O
Description
Comment
PCM_IN
66
DI
PCM data input
1.8V power domain.
If unused, keep it open.
PCM_OUT
68
DO
PCM data output
1.8V power domain.
If unused, keep it open.
PCM_SYNC
65
IO
PCM data frame
synchronization signal
1.8V power domain.
In master mode, it is an output signal.
In slave mode, it is an input signal.
If unused, keep it open.
PCM_CLK
67
IO
PCM data clock
1.8V power domain.
In master mode, it is an output signal.
In slave mode, it is an input signal.
If unused, keep it open.
I2C_SDA
42
OD
I2C serial data
An external pull-up resistor is required.
If unused, keep it open.
I2C_SCL
43
OD
I2C serial clock
An external pull-up resistor is required.
If unused, keep it open.
I2S_MCLK
152
DO
Clock output
Provide a digital clock output for an
external audio codec.
If unused, keep it open.