Wi-Fi&Bluetooth Module Series
FC64E_Hardware_Design
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Table 11: Pin Definition of PCM Interface
The following figure shows the PCM interface connection between the module and the host.
Figure 9: PCM Interface Connection
3.7. Other Interfaces
3.7.1. WLAN_SLP_CLK
The 32.768 kHz clock is used in low power modes, such as IEEE power saving mode and sleep mode. It
serves as a timer in various power saving schemes, and to maintain basic logic operations when the
module is in sleep mode.
Figure and table below show the sleep clock reference input clock requirements.
Pin Name
Pin No.
I/O
Description
Comment
PCM_DIN
44
DI
PCM data input
1.8 V power domain.
PCM_SYNC
42
DI
PCM data frame sync
PCM_CLK
45
DI
PCM clock
PCM_DOUT
43
DO
PCM data output
