LTE-A Module Series
EM121R-GL Hardware Design
EM121R-GL Hardware Design 48 / 80
1
2
255
256
125
μ
s
PCM_CLK
PCM_SYNC
MSB
MSB
LSB
PCM_DOUT
MSB
MSB
LSB
PCM_DIN
Figure 26: Primary Mode Timing
1
2
31
32
125
μ
s
PCM_CLK
PCM_SYNC
MSB
MSB
LSB
PCM_DOUT
MSB
MSB
LSB
PCM_DIN
Figure 27: Auxiliary Mode Timing
The following table shows the pin definition of PCM interface which can be applied to audio codec design.
Table 20: Pin Definition of PCM Interface
Pin No. Pin Name
I/O
Description
DC Characteristics
20
PCM_CLK
DIO, PD
PCM clock
1.8 V
22
PCM_DIN
DI, PD
PCM data input
1.8 V
24
PCM_DOUT
DO, PD
PCM data output
1.8 V
28
PCM_SYNC
DIO, PD
PCM data frame sync
1.8 V