LTE-A Module Series
EM121R-GL Hardware Design
EM121R-GL Hardware Design 46 / 80
Table 19: PCIe Reset Timing
4.3.3.4. PCIe Modern Standby Timing
EM121R-GL supports D3 Hot and D3 Cold state in Win 10 system. When the module enters D3 Hot or D3
Cold state, the timing is shown below:
⚫
D3 Hot Timing
In D3 Hot state, PCIE_RST_N remains at high level.
VCC(H)
RESET#(H)
FULL_CARD_POWER_OFF#(H)
PCIE_RST_N(H)
Module State
D3 hot
D0
D0
Figure 24: PCIe D3 Hot State Timing
⚫
D3 Cold Timing
The module must go through D3 Hot before entering D3 Cold state. In D3 Hot state, PCIE_RST_N
remains at high level, then in D3 cold state, PCIE_RST_N should be pulled down.
Index
Min.
Typ.
Max.
Comment
T1
20 ms
-
-
PCIe interface is disabled by asserting PCIE_RST_N.
T2
0 ms
-
-
Module is reset by asserting RESET#.
T3
0 ms
-
-
T3 could be ignored.
T4
100 ms
-
-
De-assert PCIE_RST_N 100 ms after de-asserting RESET#.
T5
250 ms
500 ms
-