LTE-A Module Series
EM121R-GL Hardware Design
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4.3.3. PCIe Timing
The following figure is PCIe power-on timing sequence for an adapter powered from system power rail in
PCI Express M.2 specification.
Figure 20: PCIe Power-on Timing Requirements of M.2 Specification
The following table is power-on timing variables in PCI Express M.2 specification.
Table 16: Power-up Timing of M.2 Specification
4.3.3.1. PCIe Turn-on Timing
If FULL_CARD_POWER_OFF# is de-asserted, the module will turn on. RESET# is pulled up inside the
module. Keep RESET# floating or at high level during module power-on.
PCIe turn-on timing is illustrated by the following figure.
Symbol
Min.
Typ.
Max.
Comment
T
PVPGL
50 ms
-
-
Power valid to PERST# input inactive
T
PERST#-CLK
1
00 μs
-
-
REFCLK stable before PERST# inactive