LTE Module Series
EG21-G Hardware Design
EG21-G_Hardware_Design 47 / 100
Table 15: Pin Definition of SD Card Interface
Pin Name
Pin No. I/O
Description
Comment
SDC2_DATA3
28
IO
SD card SDIO bus DATA3
SDIO signal level can be
selected according to SD
card supported level,
please refer to SD 3.0
protocol for more details.
If unused, keep it open.
SDC2_DATA2
29
IO
SD card SDIO bus DATA2
SDC2_DATA1
30
IO
SD card SDIO bus DATA1
SDC2_DATA0
31
IO
SD card SDIO bus DATA0
SDC2_CLK
32
DO
SD card SDIO bus clock
SDC2_CMD
33
IO
SD card SDIO bus command
VDD_SDIO
34
PO
SD card SDIO bus pull up power
1.8V/2.85V configurable.
Cannot be used for SD
card power. If unused,
keep it open.
SD_INS_DET
23
DI
SD card insertion detection
1.8V power domain.
If unused, keep it open.
The following figure shows a reference design of SD card.
SD Card Connector
DAT2
CD/DAT3
CMD
VDD
CLK
VSS
DAT0
DAT1
DETECTIVE
Module
SDC2_DATA3
SDC2_DATA2
SDC2_DATA1
VDD_SDIO
SDC2_DATA0
SDC2_CLK
SDC2_CMD
SD_INS_DET
R1 0R
R7
NM
R8
NM
R9
NM
R10
NM
R11
NM
R12
470K
VDD_EXT
VDD_3V
R2 0R
R3 0R
R4 0R
R5 0R
R6 0R
C2
NM
D2 C3
NM
D3 C4
NM
D4 C5
NM
D5
C6
NM
D6
C1
NM
D1
C7
10pF
D7
C8
33pF
C9
100nF
C10
100uF
+
Figure 25: Reference Circuit of SD Card
In SD card interface design, in order to ensure good communication performance with SD card, the
following design principles should be complied with:
SD_INS_DET must be connected.
The voltage range of SD card power supply VDD_3V is 2.7V~3.6V and a sufficient current up to 0.8A