LTE-A Module Series
EG060V-EA Hardware Design
EG060V-EA_Hardware_Design 54 / 82
3.20. SPI Interface
EG060V-EA provides one SPI interface which only supports master mode with a maximum clock
frequency up to 50 MHz.
The following table shows the pin definition of SPI interface.
Table 24: Pin Definition of SPI Interface
The figure below shows the timing of SPI interface. The related parameters of SPI timing are shown in the
following table.
SPI_CS_N
SPI_CLK
SPI_MOSI
MSB
1
2
SPI_MISO
3
T
t(mov)
4
t(mis)
t(mih)
t(ch) t(cl)
Figure 28: SPI Interface Timing
Table 25: Parameters of SPI Interface Timing
Pin Name
Pin No.
I/O
Description
Comment
SPI_CS
166
DO
SPI chip select
1.8 V power domain.
If unused, keep them open.
SPI_MOSI
163
DO
SPI master-out
SPI_MISO
165
DI
SPI master-in
SPI_CLK
164
DO
SPI clock
Item
Description
Min.
Typ.
Max.
Unit
T
SPI clock period
20.0
-
-
ns
t(ch)
SPI clock high level time
9.0
-
-
ns
