EC2x&EG2x-G Series
PCB Design Guideline
LTE Standard Module Series
Rev.Quectel_EC2x&EG2x-G_Series_PCB_Design_Guideline_V1.0
Date: 2020-07-23
Status: Released
www.quectel.com
Страница 1: ...EC2x EG2x G Series PCB Design Guideline LTE Standard Module Series Rev Quectel_EC2x EG2x G_Series_PCB_Design_Guideline_V1 0 Date 2020 07 23 Status Released www quectel com ...
Страница 2: ... INCURRED BY USE OF OR RELIANCE UPON THE INFORMATION ALL INFORMATION SUPPLIED HEREIN IS SUBJECT TO CHANGE WITHOUT PRIOR NOTICE DISCLAIMER WHILE QUECTEL HAS MADE EFFORTS TO ENSURE THAT THE FUNCTIONS AND FEATURES UNDER DEVELOPMENT ARE FREE FROM ERRORS IT IS POSSIBLE THAT THESE FUNCTIONS AND FEATURES COULD CONTAIN ERRORS INACCURACIES AND OMISSIONS UNLESS OTHERWISE PROVIDED BY VALID AGREEMENT QUECTEL ...
Страница 3: ...tandard Module Series EC2x EG2x G Series PCB Design Guideline EC2x EG2x G_Series_PCB_Design_Guideline 2 37 About the Document Revision History Version Date Author Description 1 0 2020 07 23 Lim PENG Initial ...
Страница 4: ...BAT 11 3 2 PWRKEY RESET_N 13 3 3 USB Interface 14 3 3 1 USB_DM USB_DP Signals 14 3 3 2 USB_VBUS Signal 16 3 4 Ethernet PHY 17 3 4 1 SGMII Interface 17 3 4 2 Ethernet Components 19 3 5 Audio Interfaces 20 3 5 1 PCM Interface 20 3 5 2 Codec Microphone Speaker 21 3 6 SD Card Interface 23 3 7 WLAN Interface 25 3 8 U SIM Interface 27 3 9 ADC Interface 28 3 10 GPIOs 29 3 11 Antenna Interfaces 30 3 11 1 ...
Страница 5: ...Guideline EC2x EG2x G_Series_PCB_Design_Guideline 4 37 Table Index Table 1 Applicable Modules 6 Table 2 Recommended Values of W and S for 50 Ω Coplanar Waveguide under Different PCB Structures 31 Table 3 Related Documents 36 Table 4 Terms and Abbreviations 36 ...
Страница 6: ...ce PCB Layout of SGMII Interface EVB 3rd Layer 19 Figure 18 Layout of Recommended 4 7 μH Inductor GND and Traces of AR8033 EVB 1st Layer 20 Figure 19 Overview of PCM Signal Traces TE A 3rd Layer 21 Figure 20 Overview of Codec ALC5616 EVB 1st Layer 22 Figure 21 Overview of Analog Audio Signal Traces EVB 1st Layer 23 Figure 22 Overview of SD Card Signal Traces EVB 1st Layer 24 Figure 23 Overview of ...
Страница 7: ...roduction This document mainly introduces the PCB reference design for Quectel LTE Standard EC2x EG2x G series modules and it takes EC25 TE A FC20 TE A and UMTS LTE EVB as examples 1 1 Applicable Modules Table 1 Applicable Modules Module Series Module EC2x series EC21 series EC25 series EC20 R2 1 EG2x G EG21 G EG25 G ...
Страница 8: ...o boarding an aircraft Please consult the airline staff for more restrictions on the use of wireless devices on an aircraft Wireless devices may cause interference on sensitive medical equipment so please be aware of the restrictions on the use of wireless devices when in hospitals clinics or other healthcare facilities Cellular terminals or mobiles operating over radio signals and cellular networ...
Страница 9: ...int is of the latest version provided by Quectel For specific footprint of each module please refer to document 1 2 3 or 4 Do not design pads 73 84 and do not route the keepout area with any traces or copper VABT VABT Antenna interfaces Antenna interfaces WLAN interface WLAN interface SD card interface SD card interface USB interface USB interface SGMII interface SGMII interface Keepout area Keepo...
Страница 10: ...ssible for high speed signal traces SGMII SDIO and USB interfaces since vias will affect the continuity of the impedance Route the differential pair traces on the same layer To minimize the signal return path the GND vias for signals such as USB SDIO SGMII PWRKEY and RESET_N should be close to the vias when the traces change layers VABT VABT Antenna Interfaces Antenna Interfaces Other signals e g ...
Страница 11: ...ve spacing for shielding frame Place the capacitor and inductor for the DC DC converter as close as possible to the corresponding pins of the DC DC converter to minimize the loop area Place output capacitors near input capacitors to share common ground area on outer layers Provide adequate thermal relief area at the gound area on outer layers along with any additional inner ground planes DC DC Con...
Страница 12: ...d its trace width is recommended to be no less than 2 mm The maximum current consumption of VABT_BB is 0 8 A and its trace width is recommended to be no less than 1 mm Moreover please pay attention to the capability and quantity of vias in the traces The GND vias of the filter capacitors for VBAT should be drilled down to the nearest main ground VBAT_RF VBAT_RF GND GND GND GND GND GND VBAT_BB VBAT...
Страница 13: ... crossing with them A layer with VBAT traces and reference ground plane is recommended When a power plane is used a complete ground plane should be added in adjacent layer as the reference plane TVS GND Figure 6 Traces of VBAT with a TVS TE A 4th Layer VABT VABT Antenna Interfaces Antenna Interfaces WLAN interface WLAN interface SD card interface SD card interface USB interface USB interface SGMII...
Страница 14: ...KEY RESET_N PWRKEY and RESET_N signal traces are recommended to be surrounded with ground If filter capacitors for PWRKEY and RESET_N are required put them near the two pins PWRKEY GND GND RESET Figure 8 PWRKEY and RESET_N Traces TE A 1st Layer PWRKEY GND GND GND RESET_N Figure 9 PWRKEY and RESET_N Traces TE A 3rd Layer ...
Страница 15: ...mended to be routed on the inner layer with the differential impedance controlled to 90 Ω Keep the spacing and length between traces comparatively equal with the length tolerance less than 2 mm and the total length less than 120 mm When a TVS needs to be added for USB_DP and USB_DM signal traces it should be close to USB connector and the junction capacitance of the TVS should be less than 2 pF TE...
Страница 16: ...ndard Module Series EC2x EG2x G Series PCB Design Guideline EC2x EG2x G_Series_PCB_Design_Guideline 15 37 USB_DM DP USB_DM DP GND GND GND GND GND GND Figure 11 Overview of USB_DM DP Signal Traces EVB 3rd Layer ...
Страница 17: ...detection signal with maximum current of 1 mA In general a trace width of 0 1 mm is sufficient TE A interface TE A interface GND GND GND GND GND GND Test points Test points USB connector USB connector USB_VBUS USB_VBUS Figure 12 Overview of USB_VBUS Signal Trace EVB 1st Layer USB_VBUS GND GND GND Figure 13 Overview of USB_VBUS Signal Trace EVB 3rd Layer ...
Страница 18: ...nal traces should also be at least 3 times wider than SGMII traces Keep the maximum length of the SGMII signal traces less than 10 inches and the difference between signals of the differential pairs SGMII_TX_P and SGMII_TX_M SGMII_RX_P and SGMII_RX_M less than 20 mil The differential impedance of SGMII signal traces is 100 Ω 10 and the reference ground of the area should be complete The series cap...
Страница 19: ... G Series PCB Design Guideline EC2x EG2x G_Series_PCB_Design_Guideline 18 37 SGMII_RST SGMII_INT SGMII_DATA SGMII_CLK SGMII_TX_M SGMII_TX_P SGMII_RX_P SGMII_RX_M GND GND GND GND GND Figure 15 Overview of SGMII Signal Traces TE A 3rd Layer ...
Страница 20: ...second layer is strongly recommended for 3 3 V and 2 5 V power supply traces and ground plane The third layer should be a reference ground The fourth layer is used for main signal traces Crystals Crystals Keepout area Keepout area AR8033 AR8033 SGMII signal traces SGMII signal traces GND GND GND GND GND GND GND GND GND GND Figure 16 Recommended PCB Layout of SGMII Interface TE A 4th Layer SGMII_IN...
Страница 21: ... AR8033 pins Network transformer Network transformer 4 7 μH inductor 4 7 μH inductor GND GND GND GND GND GND GND GND GND GND RJ45 RJ45 GND GND 1 mm 1 mm Figure 18 Layout of Recommended 4 7 μH Inductor GND and Traces of AR8033 EVB 1st Layer 3 5 Audio Interfaces 3 5 1 PCM Interface The filter capacitors for PCM_CLK PCM_SYNC should be placed close to the two pins The PCM bus is recommended to be rout...
Страница 22: ...gure 19 Overview of PCM Signal Traces TE A 3rd Layer 3 5 2 Codec Microphone Speaker The codec should be kept away from interference sources such as high power components power sources CPU DRAM Flash PMU LCD RF antennas and other high frequency components isolated and close to one of the edges or corners of the board and could be shielded if there is sufficient space ...
Страница 23: ... All MIC and SPK signal traces should be routed with total grounding and far away from interference sources The spacing between MIC_P and MIC_N should be more than 0 25 mm To avoid cross talk the spacing between the differential pair traces should exceed 1 5 mm To avoid interference between different MIC traces MIC1 and MIC2 traces should be routed on different layers as much as possible For signa...
Страница 24: ...signals etc as well as noisy signals such as clock and DC DC signals etc Keep the impedance of SDIO signal traces at 50 Ω 10 maintaining the integrity of the reference plane SD_CLK and SD_CMD should be surrounded with ground on the layer and ground planes above and below If limited by space the SD_DATA0 to SD_DATA3 could be surrounded with ground together The total length of each SDIO signal trace...
Страница 25: ...races SD card traces GND GND GND GND GND GND GND GND GND GND TVS Capacitors Resistors TVS Capacitors Resistors SD Card connector SD Card connector Figure 22 Overview of SD Card Signal Traces EVB 1st Layer SD_CLK GND GND GND GND GND SD_CMD SD_INS_DET VDD_SDIO SD_DATA Figure 23 Overview of SD Card Signal Traces EVB 3rd Layer ...
Страница 26: ...nce between them should be less than 1 mm The load capacitance for SD card signal traces should be less than 15 pF Keep the impedance of SDIO signal traces at 50 Ω 10 maintaining the integrity of the reference plane SD_CLK and SD_CMD should be surrounded with ground on the layer and adjacent ground planes If limited by space the SD_DATA0 to SD_DATA3 could be surrounded with ground together SDIO_CL...
Страница 27: ... G Series PCB Design Guideline EC2x EG2x G_Series_PCB_Design_Guideline 26 37 SD_CLK SD_CLK GND GND GND GND GND GND GND GND GND GND SD_CMD SD_CMD VDD_1V8 VDD_1V8 SD_DATA SD_DATA Figure 25 Overview of SDIO Signal Traces FC20 TE A 3rd Layer ...
Страница 28: ...nce between each other The peripheral components such as TVS capacitors and resistors should be put near the U SIM card connector U SIM interface U SIM interface GND GND GND GND GND GND GND GND GND GND TVS Capacitors Resistors TVS Capacitors Resistors U SIM card connector U SIM card connector Figure 26 Overview of U SIM Signal Traces EVB 1st Layer USIM_PRESENCE GND GND GND GND GND USIM_VDD USIM_RS...
Страница 29: ...EG2x G Series PCB Design Guideline EC2x EG2x G_Series_PCB_Design_Guideline 28 37 3 9 ADC Interface All ADC signal traces should be surrounded with ground GND GND GND GND ADC0 ADC1 Figure 28 Overview of ADC Signal Traces EVB 3rd Layer ...
Страница 30: ..._Design_Guideline 29 37 3 10 GPIOs Keep GPIO traces away from interference signals such as clock RF and power supplies etc Filter capacitors need to be added and be placed close to the module when GPIO is used as the input Figure 29 Overview of GPIO Signal Traces TE A without Copper Pouring ...
Страница 31: ...p Waveguide Figure 30 PCB Structure of Microstrip Waveguide 3 11 1 2 PCB Structure of Coplanar Waveguide Factors affecting impedance include dielectric constant usually 4 2 4 6 here 4 4 dielectric layer height H RF trace width W the spacing between RF traces and the ground S and copper thickness T When T 0 035 mm the following table lists the recommended values of W and S for 50 Ω coplanar wavegui...
Страница 32: ...de Table 2 Recommended Values of W and S for 50 Ω Coplanar Waveguide under Different PCB Structures Dielectric Height H RF Trace Width W Spacing Between RF Trace and The Ground S 0 076 mm 0 1188 0 15 mm 0 1 mm 0 1623 mm 0 2 mm 0 15 mm 0 24 mm 0 2 mm 0 8 mm 0 8 mm 0 18 mm 1 0 mm 0 8 mm 0 17 mm 1 2 mm 0 8 mm 0 16 mm 1 6 mm 0 8 mm 0 15 mm 2 mm 0 8 mm 0 14 mm ...
Страница 33: ... typically used in RF layout to control characteristic impedance If there is a 2 layer PCB the top layer is used for signal trace routing and the bottom layer should be the reference ground layer as shown in Figure 32 If there is a 4 layer PCB the reference ground layer can be the second the third or the fourth layer If the third layer is selected as the ground layer the second layer should be kep...
Страница 34: ...orresponding to the marks in the following two figures respectively 1 Control the trace width W and the spacing between RF traces and grounds S corresponding to the 50 Ω coplanar waveguide Taking common PCB board with FR4 medium dielectric constant 4 2 and copper thickness of 35 μm as an example the W and S corresponding to the thickness between different signal layers and reference grounds are sh...
Страница 35: ... 5 Make sure that reference ground planes corresponding to RF traces are complete Increase the number of GND vias for current reflow of RF signal and the spacing between GND vias and RF traces should be more than two times of trace width Keep the ground plane area for RF traces within the same layer be as large as possible and the reference ground plane in the other layer complete as well Besides ...
Страница 36: ...E Standard Module Series EC2x EG2x G Series PCB Design Guideline EC2x EG2x G_Series_PCB_Design_Guideline 35 37 4 Thermal Design For more details of the thermal design of the PCB please refer to document 5 ...
Страница 37: ...nput Output LTE Long Term Evolution PCB Printed Circuit Board PCM Pulse Code Modulation PHY Physical Layer RF Radio Frequency SD Secure Digital SN Document Name Remark 1 Quectel_EC21_Footprint Part EC21 series Footprint Part 2 Quectel_EC25_Footprint Part EC25 series Footprint Part 3 Quectel_EC20_R2 1_Footprint Part EC20 R2 1 Footprint Part 4 Quectel_EG25 G EG21 G_Footprint Part EG25 G EG21 G Footp...
Страница 38: ...ies PCB Design Guideline EC2x EG2x G_Series_PCB_Design_Guideline 37 37 SGMII Serial Gigabit Media Independent Interface USB Universal Serial Bus U SIM Universal Subscriber Identity Module VBAT Voltage at Battery WLAN Wireless Local Area Network ...
