LPWA Module Series
BC950N-N1 Hardware Design
3.2. Pin Assignment
Power
ANT
GND
UART
USIM
SI M_GND
SI M_CLK
SI M_DATA
SI M_RST
SI M_VDD
AD
C
*
R
ESE
R
VED
VD
D
_
EX
T
PWRKEY
RESET
NE
T
L
IG
HT
Top View
GN
D
RF
_
AN
T
VB
AT
VCC_BT*
GN
D
GN
D
GN
D
GN
D
VB
AT
TXD
RXD
RI
SWDIO_BT*
SWDCLK_BT*
TXD_BT*
RXD_BT*
R
XD
_
D
BG
T
XD
_
D
BG
PS
M
_
E
INT
Other
2
3
4
5
6
7
8
9
10
11
12
13
14
1
7
1
8
1
9
2
0
2
3
2
7
2
6
2
5
2
4
2
2
2
1
5
4
5
3
5
2
5
1
4
8
4
4
4
5
4
6
4
7
15
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
GND
BC950N-N1
5
0
4
9
USB
55
75
56
76
57
77
58
78
59
79
60
80
90
70
89
69
88
68
87
67
86
66
85
65
74
73
94
93
72
71
92
91
81
82
61
62
83
84
63
64
RXD _A UX
TX D_A UX
USB _3V3
USB _DM
USB _DP
RESERVED
1
16
28
43
GND
R
ESE
R
VED
R
ESE
R
VED
R
ESE
R
VED
RESERVED
RESERVED
RESERVED
RESERVED
GND
RESERVED
RESERVED
CTS_A UX
RTS_A UX
USB _MO DE
R
ESE
R
VED
R
ESE
R
VED
RES E RV ED
RES E RV ED
RES E RV ED
RES E RV ED
RES E RV ED
RES E RV ED
GND
GND
RES E RV ED
GND
GND
GND
GND
GND
GND
GND
GND
GND
RES E RV ED
GND
GND
GND
GND
GND
GND
GND
RES E RV ED
R
ESE
R
VED
R
ESE
R
VED
GP IO1_B T*
GP IO2_B T*
RES E T_B T*
GP IO3_B T*
GP IO4_B T*
BT_ANT*
RESERVED
RESERVED
RESERVED
RESERVED
ADC*
RESERVED
RESERVED
Figure 2: Pin Assignment
1. Keep all reserved pins unconnected.
2. “*” means under development.
NOTES
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