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QM_XC7A35T_SDRAM Core Board

User Manual V02

2.1

Install Development Tools

The QM_XC7A35T_SDRAM core board tool chain consists of Xilinx Vivado 2016.4, Xilinx USB platform cable,

XC7A35T core board and 5V DC power supply. Below image shows the Xilinx Vivado 2016.4 development

environment which could be downloaded from

Figure 2-3. Vivado 2016.4

Below image shows the JTAG connection between Xilinx USB platform cable and XC7A35T core board:

Figure 2-4. JTAG Connection and Power Supply

TMS      (Green)
TDI       (Purple)
TDO      (White)
TCK    (Yellow)
GND      (Black)
VREF       (Red)

5V DC

Содержание XC7A35T SDRAM

Страница 1: ...trate the highest performance per watt fabric transceiver line rates DSP processing and AMS integration in a cost optimized FPGA Featuring the MicroBlaze soft processor and 1 066Mb s DDR3 support the...

Страница 2: ...T_SDRAM HARDWARE DESIGN 6 2 2 1 QM_XC7A35T_SDRAM Power Supply 6 2 2 2 QM_XC7A35T_SDRAM SPI Boot 7 2 2 3 QM_XC7A35T_SDRAM Memory 8 2 2 4 QM_XC7A35T_SDRAM System Clock 8 2 2 5 QM_XC7A35T_SDRAM Extension...

Страница 3: ...oard FPGA XC7A35T 1FTG256C On Board FPGA external crystal frequency 50MHz XC7A35T 1FTG256C has rich block RAM resource up to 1 800Kb XC7A35T 1FTG256C has 33 280 logic cells On Board N25Q064 SPI Flash...

Страница 4: ...d The QM_XCA35T_SDRAM core board includes below item Figure 2 1 QM_XC7A35T_SDRAM Top View Below image shows the dimension of the QM_XC7A35T_SDRAM core board 6 7cm x 8 4cm The unit in below image is mi...

Страница 5: ...core board and 5V DC power supply Below image shows the Xilinx Vivado 2016 4 development environment which could be downloaded from Xilinx office website Figure 2 3 Vivado 2016 4 Below image shows the...

Страница 6: ...8 C22 100NF C20 100NF C21 100NF C19 100NF 1V0 C18 10V 4 7uF C35 10V 4 7uF C37 100NF C36 100NF 3V3 1V0 C74 10V 4 7uF C76 100NF C75 100NF VCCO_34_35 C61 10V 4 7uF C62 100NF XADC is not used C63 100NF C2...

Страница 7: ...ware Settings The LED D2 will be turned on after the FPGA successfully loading configuration file from SPI Flash during power on stage In this case LED D2 could be used as FPGA loading status indicato...

Страница 8: ...re 2 10 50MHz System Clock DQML A8 A9 SD_NCS0 A13 D2 A6 D4 A11 A4 D10 A14 CAS A1 D5 D12 D15 D9 D14 C4 100NF SDCLK0 C7 100NF C8 100NF C9 100NF C6 100NF C5 100NF MT48LC16M16A2 MN1 A0 23 A1 24 A2 25 A3 2...

Страница 9: ...NK35_C2 BANK35_D5 BANK35_E5 BANK35_D3 BANK35_D1 BANK35_K5 BANK35_E6 BANK35_C6 BANK35_C7 BANK35_G4 BANK35_G5 BANK35_J5 BANK35_J4 BANK34_L4 BANK34_M4 BANK34_N3 BANK34_N2 5V_IN 5V_IN BANK14_M12 BANK14_N9...

Страница 10: ...The on board JTAG port uses 6P 2 54mm pitch header which could be easily connected to Xilinx USB platform cable Below image shows the hardware design of the JTAG port Figure 2 13 JTAG Port 2 2 3 QM_XC...

Страница 11: ...XC7A35T_SDRAM Core Board User Manual V02 2 2 4 QM_XC7A35T_SDRAM User Key Below image shows the PROGRAM_B key and one user key Figure 2 15 Keys 3V3 SW1 1 2 PROG_B SW2 1 2 BANK15_A8 R221 4 7k R228 4 7k...

Страница 12: ...35T_SDRAM Core Board User Manual V02 3 Reference 1 ug470_7Series_Config pdf 2 ds181_Artix_7_Data_Sheet pdf 3 ug475_7Series_Pkg_Pinout pdf 4 n25q_64a_3v_65nm pdf 5 MT48LC16M16 pdf 6 MP2359 pdf 7 NCP152...

Страница 13: ...QM_XC7A35T_SDRAM Core Board User Manual V02 4 Revision Doc Rev Date Comments 0 1 05 10 2017 Initial Version 1 0 05 14 2017 V1 0 Formal Release 2 0 18 02 2018 Update PCB color to black...