DG Series Datasheet
Страница 1: ...DG Series Datasheet ...
Страница 2: ...Revision History Revision No History Draft Date Remark A 0 First document announced 01 26 05 Preliminary ...
Страница 3: ...s 1 3 Introduction 2 4 Revision History 2 5 Specification 3 6 Installation Guide 5 7 Block Diagram 7 8 Pin Signal Assignment 9 9 Interface Signal Assignments 10 10 Signal Description 11 11 Interface Register Definition 13 12 Physical Outline 16 ...
Страница 4: ... is possible to operate good performance for the portable system which have IDE interface slots Features High Performance Non volatile Flash Memory The DOM is implemented by using NAND type flash memory which is a high density non volatile read write device Flash data retention is guaranteed for at least 10 years with no battery or other power source required 100 True IDE Mode HDD Compatible Broad...
Страница 5: ...is suitable for use in portable and embedded systems which have limited space and power consumption Unlike standard IDE drives no signal cable and extra special space is required The DiskOnModule is a solid state solution for IDE Hard Disk drive which has no moving parts That provides a good stability in a moving system The DiskOnModule products are also free from extra and special algorithm or so...
Страница 6: ...ing 1000G 1000G Configuration Capacity 16Mbytes to 1 5Gbytes Sector size 512bytes System Performance Media transfer rate note1 Read 4 3 MB sec Write 3 3 MB sec Interface burst transfer rate PIO mode 2 8 3 MB sec Reliability MTBF 1 000 000 hours ECC 22bit per 256bytes Power Requirement Voltage DC 3 3V 5 DC 5 0V 10 Power Consumption Read 30mA typ Write 28mA typ Stand by 3mA typ note1 There will be d...
Страница 7: ...inder Head Sector Total sectors 16MB 1000 2 16 32000 32MB 500 8 16 64000 64MB 500 8 32 128000 128MB 500 16 32 256000 192MB 750 16 32 384000 256MB 1000 16 32 512000 512MB 1015 16 63 1023120 1024MB 2031 16 63 2047248 1536MB 3047 16 63 3071376 ...
Страница 8: ...y pressing a special key such as DELETE ESC or F1 during startup See your computer manual for details Press the appropriate key to run the system setup program 2 If your BIOS provides automatic drive detection an AUTO drive type select this option If you use Normal CHS mode to partition your DOM you can get the maximum formatted capacity This allows your computer to configure itself automatically ...
Страница 9: ...er drive C make sure that the partition is marked active 6 Create an extended partition and additional logical drives as necessary until all the space on your new hard drive has been partitioned 7 When the partitioning is complete FDISK reboots your computer Caution Make sure to use the correct drive letters so that you do not format a drive that already contains data 8 At the A prompt type format...
Страница 10: ...lash Controller DATA BUFFER DATA FLASH ARRAY Regulator X tal Control signal Flash memory bus ATA IDE Interface Vcc Hvcc DD0 to DD15 CS0 CS1 RESET DA0 to DA2 DIOR DIOW INTRQ IORDY DASP PDIAG Master Slave External Option ...
Страница 11: ...ement in flash memory the life of the device will be longer than the device without it When all of the reserved blocks have replaced the bad blocks the device will be locked automatically to prevent programming but the data can still be read out for back up Because the block of flash memory has a limited life when the host writes data in the same address PQI DiskOnModule does not to program data i...
Страница 12: ...1 12 12 DD12 DD2 13 13 14 14 DD13 DD1 15 15 16 16 DD14 DD0 17 17 18 18 DD15 Ground 19 19 20 20 keypin or Vcc DMARQ 21 21 22 22 Ground DIOW 23 23 24 24 Ground DIOR 25 25 26 26 Ground IORDY 27 27 28 28 CSEL DMACK 29 29 30 30 Ground INTRQ 31 31 32 32 reserved DA1 33 33 34 34 PDIAG DA0 35 35 36 36 DA2 CS0 37 37 38 38 CS1 DASP 39 39 40 40 Ground 5 V logic see note 41 41 42 42 5 V Motor see note Ground ...
Страница 13: ...ription Host Dir Dev Acronym Cable select see note CSEL Chip select0 CS0 Chip select1 CS1 Data bus bit 0 Data Bus bit 15 DD0 DD15 Device active or slave Device 1 present see note DASP Device address bit 0 DA0 Device address bit 1 DA1 Device address bit 2 DA2 DMA acknowledge DMACK DMA request DMARQ Interrupt request INTRQ I O read DIOR I O ready IORDY I O write DIOW Passed diagnostics see note PDIA...
Страница 14: ...the read strobe signal from the host The falling edge of DIOR enables data from the device onto the signals DD 7 0 or DD 15 0 The rising edge of DIOR latches data at the host and the host shall not act on the data until it is latched DIOW Device I O write This is the Write strobe signal from the host This rising edge of DIOW latches data from the signals DD 7 0 or DD 15 0 into the device The devic...
Страница 15: ...Write when the device is not ready to respond to a data transfer request If actively asserted the signal only be enabled during DIOR DIOW cycles to the selected device If open collector when IORDY is not negated it shall be in the high impedance undriven state This use of IORDY is required for PIO modes 3 and above and otherwise optional PDIAG Passed diagnostics This signal shall be asserted by De...
Страница 16: ...DIAG Devices are selected by the DEV bit in the Device Head register When the DEV bit is equal to zero Device 0 is selected When the DEV bit is equal to one Device 1 is selected When devices are daisy chained one shall be set as Device 0 and the other as Device 1 I O register descriptions Communication to or from the device is through an I O Register that routes the input or output data to or from...
Страница 17: ... LBA 27 24 see note 2 Device Head LBA 27 24 see note 2 A N 1 1 1 Status Command A A Invalid address Invalid address Key A signal asserted N signal negated don t care NOTES_ 1 This register is obsolete It is recommended that a device not respond to a read of this address If a device does respond it shall not drive the DD7 signal to prevent possible conflict with floppy disk implementations 2 Mappin...
Страница 18: ...uplicate Data register D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Data Word Odd Data Byte Only Even or Even Odd Data Byte Duplicate registers Access Data register CE2 CE A0 Offset Data Bus Word Data register 0 0 0 0h 8h D15 D0 Word Data register 0 0 1 1h 9h D15 D0 Even Byte Data register 1 0 0 0h 8h D7 D0 Odd Byte Data register 1 0 1 9h D7 D0 Odd Byte Data register 0 1 8h 9h D15 D8 Erro...
Страница 19: ...16 Physical Outline DG0XXXX44NX0 44 PIN M S A A Detail S 2 1 MASTER SALVE ...
