PEX 8619BA Base Board RDK Hardware Reference Manual – Version 1.0
Copyright © 2008 by PLX Technology, Inc. All rights reserved
24
Pin #
Signal Name
Pin #
Signal Name
18 C2n-Downstream 17
GND
20 GND 19
C3p-Upstream
22 C3p-Downstream 21
C3n-Upstream
24 C3n-Downstream 23
GND
26 GND 25
C4p-Upstream
28 C4p-Downstream 27
C4n-Upstream
30 C4n-Downstream 29
GND
32 GND 31
C5p-Upstream
34 C5p-Downstream 33
C5n-Upstream
36 C5n-Downstream 35
GND
38 GND 37
C6p-Upstream
40 C6p-Downstream 39
C6n-Upstream
42 C6n-Downstream 41
GND
44 GND 43
C7p-Upstream
46 C7p-Downstream 45
C7n-Upstream
48 C7n-Downstream 47
G2 GND
4.3.10 PEX 8619 I
2
C Port (JP8)
Table 18. Pin assignment of JP8
Pin Number
Signal Name
1 I2C_SCL0
2 GND
3 I2C_SDA0
4 NC
4.3.11 Debug Signal Header (JP9 & JP11)
This is for PLX use only.
Table 19. Pin assignment of JP9 & JP11
Pin #
Signal Name at JP9
Signal Name at JP11
1 -
-
3 GND
GND
5 -
NC
7 GPIO16
DEBUG_SEL0
9 GPIO17
STRAP_UPCFG_TIMER_EN#
11 GPIO18
STRAP_SMBUS_EN#
13 GPIO19
STRAP_SPARE0#
15 GPIO20
UPSTRM_PSEL3
17 GPIO21
GPIO29
19 GPIO22
GPIO30