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PCI 6152 (HB1-SE)

PCI-to-PCI Bridge

Data Book

Содержание PCI 6152 33BC

Страница 1: ...PCI 6152 HB1 SE PCI to PCI Bridge Data Book...

Страница 2: ......

Страница 3: ...PCI 6152 HB1 SE PCI to PCI Bridge Data Book Version 2 0 May 2003 Website http www plxtech com Technical Support http www plxtech com support Phone 408 774 9060 800 759 3735 Fax 408 774 2169...

Страница 4: ...e PLX logo are registered trademarks of PLX Technology Inc Other brands and names are property of their respective owners These devices are not designed intended authorized or warranted to be suitable...

Страница 5: ...bit PCI interface 160 pin PQFP PCI Local Bus Specification Rev 2 2 with VPD support PCI 6152 66BC is 66 MHz capable and PCI 6152 33BC and 33PC run at 33 MHz Synchronous primary and secondary PCI bus o...

Страница 6: ...Enhanced EEPROM Section description 2 0 05 28 03 This release reflects PLX part numbering Changed SRST_L to S_RST_L 3 places in Register 3Eh Changed Register 82h bits 11 15 description Changed Dual Ad...

Страница 7: ...ION SPACE MAP TRANSPARENT MODE 24 7 2 CONFIGURATION REGISTER DESCRIPTION 26 8 PCI BUS OPERATION 45 8 1 TYPES OF TRANSACTIONS 45 8 2 ADDRESS PHASE 46 8 3 DEVICE SELECT DEVSEL_L GENERATION 46 8 4 DATA P...

Страница 8: ...BRIDGE BEHAVIOR 71 14 1 ABNORMAL TERMINATION INITIATED BY BRIDGE MASTER 72 14 1 1 Master Abort 72 14 1 2 PCI Master on Primary Bus 72 14 2 CONFIGURATION TYPE 1 TO TYPE 0 CONVERSION 72 14 3 CONFIGURATI...

Страница 9: ...93 Pin Assignment Sorted by Signal Name 95 PCI 6152 33PC VS 21152 PINOUT COMPARISON 97 APPENDIX B SAMPLE SCHEMATICS 98 APPENDIX C APPLICATION NOTES 104 PCI 6152 66BC APPLICATION NOTE 1 CONNECTING PCI...

Страница 11: ...errupt Pin Register 32 Memory Base Register 31 Memory Limit Register 31 Miscellaneous Control Register 40 41 Next Item Pointer 36 37 38 PCI 6152 Test Register 44 PMCSR Bridge Support 37 Power Manageme...

Страница 12: ...ndividual secondary port Programmable 2 level arbiter Enhanced address decoding 32 bit I O and memory address decoding Supports PCI transaction forwarding for Type 1 to Type 0 downstream only configur...

Страница 13: ..._STOP_L P_AD 31 0 P_CBE 3 0 P_PAR P_PERR_L S_FRAME_L S_IRDY_L S_TRDY_L P_IDSEL S_GNT_L 3 0 PCI 6152 Primary PCI BUS Secondary PCI BUS S_DEVSEL_L S_STOP_L S_AD 31 0 S_CBE 3 0 S_PAR S_REQ_L 3 0 S_RST_L...

Страница 14: ...S Primary command byte enables Multiplexed command field and byte enable field During address phase the initiator drives the transaction type on these pins After that the initiator drives the byte ena...

Страница 15: ...stop the current transaction Before being three stated it is driven to a deasserted state for one cycle P_IDSEL PI Primary ID Select Used as chip select line for Type 0 configuration access to PCI 615...

Страница 16: ...en by the initiator of a transaction to indicate the beginning and duration of an access The deassertion of S_FRAME_L indicates the final data phase requested by the initiator Before being three state...

Страница 17: ...es secondary clocks phase synchronous with the P_CLK 5 4 Reset Signals Name Type Description P_RST_L I Primary Reset When P_RST_L is active outputs and should be asynchronously three stated and P_SERR...

Страница 18: ...PIO 3 0 PTS General Purpose Input Output pins These 4 general purpose signals are programmable as either input only or bi directional signals by writing the GPIO output enable control register EEPCLK...

Страница 19: ...SS VSS VSS VDD VSS VSS SGNT0_L SGNT1_L SGNT2_L PAD27 GPIO2 PAD31 SRST_L PGNT_L SVIO SGNT3_L PAD24 PAD29 SCLK0 SCLK1 SCLK PAD28 SCLK2 RST_L GPIO1 SCLK3 PAD30 PCLK PAD25 SCLK4 PAD26 GOZ_L PVIO NAND_O PR...

Страница 20: ..._AD 12 TS C06 S_AD 09 TS C07 S_AD 07 TS C08 S_AD 02 TS C09 P_AD 00 TS C10 P_AD 02 TS C11 P_AD 05 TS C12 VSS P C13 P_AD 09 TS C14 EJECT I D01 S_TRDY_L STS D02 S_DEVSEL_L STS D03 S_STOP_L STS D04 VSS P...

Страница 21: ...01 S_AD 31 TS M02 S_REQ_L 0 I M03 VSS P M04 S_GNT_L 2 O M05 S_CLK I M06 S_CLK_O 1 O M07 S_CLK_O 4 O M08 P_CLK I M09 P_REQ_L O M10 P_AD 29 TS M11 P_AD 26 TS M12 VSS P M13 GPIO 3 I O M14 P_AD 23 TS N01...

Страница 22: ...27 TS P11 P_AD 28 TS M10 P_AD 29 TS N10 P_AD 30 TS P10 P_AD 31 TS A13 P_CBE_L 0 TS F12 P_CBE_L 1 TS J13 P_CBE_L 2 STS P14 P_CBE_L 3 TS M08 P_CLK I A14 P_CLKRUN_L TS H14 P_DEVSEL_L STS J14 P_FRAME_L S...

Страница 23: ...01 S_PERR_L TS M02 S_REQ_L 0 I N01 S_REQ_L 1 I P01 S_REQ_L 2 I P02 S_REQ_L 3 I P04 S_RST_L O C02 S_SERR_L I D03 S_STOP_L STS D01 S_TRDY_L STS N05 S_VIO I D06 VDD P D07 VDD P D08 VDD P D09 VDD P F04 VD...

Страница 24: ...le Memory Limit Prefetchable Memory Base 24h Prefetchable Memory Base Upper 32 Bits 28h Prefetchable Memory Limit Upper 32 Bits 2Ch I O Limit Upper 16 Bits I O Base Upper 16 Bits 30h Reserved ECP Poin...

Страница 25: ...Reserved A8h BFh Arbiter Control Reserved Miscellaneous Control Reserved C0h Reserved GPIO Control Miscellaneous Control C4h EEPROM Data EEPROM Address EEPROM control C8h Test Register Reserved CCh R...

Страница 26: ...erface 0 ignore all memory transaction 1 enable response to memory transaction Reset to 0 2 Bus Master Enable R W Controls the bridge s ability to operate as a master on the primary interface 0 do not...

Страница 27: ...52 performs address data stepping set to 1 8 P_SERR_L Enable R W Controls the enable for the P_SERR_L pin 0 disable the P_SERR_L driver 1 enable the P_SERR_L driver Reset to 0 9 Fast Back to Back Enab...

Страница 28: ...Detected R WC It is set when the following conditions are met 1 P_PERR_L is asserted 2 Bit 6 of Command Register is set Reset to 0 9 10 DEVSEL_L timing R O DEVSEL_L timing default to 01 to indicate m...

Страница 29: ...r that is subordinate to the bridge This value is set with configuration software Reset to 0 Secondary Latency Timer Read Write Offset 1Bh This register is programmed in units of PCI bus clocks Reset...

Страница 30: ...1 SPERR_L is asserted 2 Bit 6 of Command Register is set Reset to 0 9 10 DEVSEL_L timing R O Medium DEVSEL_L timing set to 01 11 Signaled Target Abort R WC Should be set by a target device whenever a...

Страница 31: ...t Register Read Write Offset 26h This register defines the upper limit address of the memory mapped address range for forwarding the cycle through the bridge The upper twelve bits correspond to addres...

Страница 32: ...warding of S_SERR_L to primary Reset to 0 2 ISA Enable R W Controls the bridge s response to ISA I O addresses which is limited to the first 64K 0 forward all I O addresses in the range defined by the...

Страница 33: ...ability to generate fast back to back transactions to different devices on the secondary interface 0 no fast back to back transaction 1 enable fast back to back transaction Reset to 0 8 11 Reserved R...

Страница 34: ...group or the low priority group 0 low priority group 1 high priority group Reset to 1 15 10 Reserved R O Reserved set to 0 s Secondary Clock Control Register Read Write Offset 68h Bit Function Type De...

Страница 35: ...un protocol enable 0 disable 1 enable Defaults to 0 2 Primary Clock Stop R W Primary clock stop 0 allow primary clock to stop if secondary clock is stopped 1 always keep primary clock running Defaults...

Страница 36: ...cription 0 2 Version R O This register is set to 001b indicating that this function complies with Rev 1 0 of the PCI Power Management Interface Specification 3 PME Clock R O This bit is a 0 indicating...

Страница 37: ...ta Select field 15 PME Status R O This bit is set to 0 since PCI 6152 does not support PME signaling PMCSR Bridge Support R W Offset 86h Bit Function Type Description 0 5 Reserved R O Reserved 6 B2 B3...

Страница 38: ...ice being extracted Writing a 1 to this bit clears the status 0 ENUM is set to 1 1 ENUM is asserted low 7 Insertion State W1TC Indicates assertion of ENUM due to the device being inserted Writing a 1...

Страница 39: ...M cycle is finished then it be set to 1 Data for reads is available at register 9ch Writing a 1 to this bit generates a write cycle to the EEPROM at the VPD address specified in bits 7 2 of this regis...

Страница 40: ...Low priority group arbitration order R W This bit is only valid when the low priority arbitration group is set to a fixed arbitration scheme If 1 priority decreases in ascending numbers of the master...

Страница 41: ...is deasserted at the same time as PGNT_L This bit defaults to 1 in Rev B and Rev BA parts 4 Secondary to Primary transaction delay R W Specify delay for transactions going from secondary to primary P...

Страница 42: ...gured as output If 0 GPIO1 is an input pin 6 GPIO1 Output Register R W Value written here will be output to GPIO1 pin if configured as output 7 Reserved R O Reserved 8 GPIO2 Input R O Contains the sta...

Страница 43: ...ed with values programmed in the EEPROM If zero EEPROM autoload was unsuccessful or was disabled 5 4 Reserved R O Reserved Returns 0 when read 7 6 EEPROM clock rate R W Controls frequency of EEPROM cl...

Страница 44: ...n 0 EEPROM Autoload control R W If 1 disables EEPROM autoload 1 Fast EEPROM Autoload R W If 1 speeds up EEPROM autoload 2 EEPROM autoload status R O Status of EEPROM autoload 3 7 Reserved R O Reserved...

Страница 45: ...ecode section Direction of AD 31 0 is determined by the combination of address decode and location of slave 8 1 Types of Transactions This section provides a summary of PCI transactions performed by P...

Страница 46: ...e nor does it respond to Type 0 configuration transactions on the secondary PCI interface The PCI to PCI Bridge Architecture Specification does not support configuration from the secondary bus 8 2 Add...

Страница 47: ...dary master access device on primary bus PCI 6152 will forward address command data byte enable S_IRDY to primary while forwarding P_DEVSEL_L P_TRDY and P_STOP to secondary 8 6 Read Transactions PCI 6...

Страница 48: ...on number is also included in both Type 0 and Type 1 formats and indicates which function of a multifunction device is to be accessed For single function devices this value is not decoded Type 1 confi...

Страница 49: ...tions are performed only in the downstream direction that is PCI 6152 generates a Type 0 transaction only on the secondary bus and never on the primary bus PCI 6152 responds to a Type 1 configuration...

Страница 50: ...00 27 Ch 01100 0001 0000 0000 0000 28 Dh 01101 0010 0000 0000 0000 29 Eh 01110 0100 0000 0000 0000 30 Fh 01111 1000 0000 0000 0000 31 1Fh 11111 Generate special cycle P_AD 7 2 00h 0000 0000 0000 0000...

Страница 51: ...lusive in the secondary bus number register and the upper limit inclusive in the subordinate bus number register The bus command is a configuration read or write transaction PCI 6152 also supports Typ...

Страница 52: ...register number in address bits AD 7 2 is equal to 000000b The bus number is equal to the value in the secondary bus number register in configuration space for downstream forwarding or equal to the va...

Страница 53: ...ondition The target can terminate transactions with one of the following types of termination Normal termination TRDY and DEVSEL_L asserted in conjunction with FRAME de asserted and IRDY asserted Targ...

Страница 54: ...peats the transaction PCI 6152 does not respond to the transaction with DEVSEL_L This passes the master abort condition back to the initiator Note When PCI 6152 performs a Type 1 to special cycle tran...

Страница 55: ...nsfer PCI 6152 receives a master abort PCI 6152 receives a target abort PCI 6152 makes 2 24 write attempts resulting in a response of target retry Table 8 3 Response to Delayed Write Target Terminatio...

Страница 56: ...al If prefetchable target disconnect only if initiator requests more data than read from target If nonprefetchable target disconnect on first data phase Target retry Reinitiate read transaction to tar...

Страница 57: ...e delayed transaction queue o The read request has already been queued but read data is not yet available o The delayed transaction queue is full and the transaction cannot be queued o A delayed read...

Страница 58: ...defined in the configuration space to specify the I O address space for downstream and upstream forwarding I O base and limit address registers The ISA enable bit The VGA mode bit The VGA snoop bit T...

Страница 59: ...O base address The bottom 4 bits read only as 1h to indicate that PCI 6152 supports 32 bit I O addressing Bits 11 0 of the base address are assumed to be 0 which naturally aligns the base address to a...

Страница 60: ...warding All other I O transactions initiated on the secondary bus are forwarded upstream only if they fall outside the I O address range When the ISA enable bit is set devices downstream of PCI 6152 c...

Страница 61: ...echanism The memory mapped I O range supports 32 bit addressing only The PCI to PCI Bridge Architecture Specification does not provide for 64 bit addressing in the memory mapped I O space The memory m...

Страница 62: ...I bus PCI 6152 de asserts P_REQ for two PCI clock cycles When P_GNT is asserted LOW by the primary bus arbiter after PCI 6152 has asserted P_REQ PCI 6152 initiates a transaction on the primary bus on...

Страница 63: ...te its own cycle by asserting STOP_L This mode can be independently enabled for the Primary to Secondary transfer and for the Secondary to Primary transfer It is used primarily to minimize the delay b...

Страница 64: ...aster abort If the parity error response bit is not set PCI 6152 proceeds normally and accepts the transaction if it is directed to or across the PCI 6152 PCI 6152 sets the detected parity error bit i...

Страница 65: ...the secondary bus the following events occur PCI 6152 asserts P_SERR two cycles following the data transfer if the secondary interface parity error response bit is set in the bridge control register...

Страница 66: ...error bit in the status register corresponding to the primary interface This bit is set when PCI 6152 detects a parity error on the primary interface Table 12 1 Setting the Primary Interface Detected...

Страница 67: ...layed write Upstream Primary x x 1 Delayed write Upstream Secondary x x 1 x don t care Table 12 3 shows setting the data parity detected bit in the status register corresponding to the primary interfa...

Страница 68: ...ster corresponding to the secondary interface must be set Table 12 4 Setting the Secondary Interface Data Parity Detected Bit Secondary data parity detected bit Transaction type Direction Bus where er...

Страница 69: ...ndary x x 1 x don t care 2 The parity error was detected on the target secondary bus but not on the initiator primary bus 3 The parity error was detected on the target primary bus but not on the initi...

Страница 70: ...following conditions is met Signal P_RST is asserted Signal S_RST remains asserted as long as P_RST is asserted and does not de assert until P_RST is de asserted The secondary reset bit in the bridge...

Страница 71: ...signals to primary except in the case of dummy arbitration Master on secondary Target on primary port PCI 6152 asserts S_DEVSEL_L then passes the cycle to the appropriate port When cycle is complete o...

Страница 72: ...secondary side except configuration cycle in the 1 clock delay case as described below PCI 6152 performs configuration type 1 to type 0 conversion on the cycle with a matched bus number It will pass t...

Страница 73: ...de 14 5 Decoding PCI 6152 uses decoding circuit to determine the slave device location During the memory cycle PCI 6152 uses Memory Base Limit and PrefetchBase Limit Slave is on the secondary side if...

Страница 74: ...de 1 0 P_CLKRUN is set high when the system s central resource wants to stop P_CLK and then PCI 6152 will either signal that it allows PCI clock to be stopped by letting P_CLKRUN remain high or it wil...

Страница 75: ...utputs PCI 6152 has 5 secondary clock outputs that can be used as clock inputs for up to 4 external secondary bus devices with one feedback to S_CLK The rules for using secondary clocks are Each secon...

Страница 76: ...ry to configure PCI 6152 66BC as a 66 MHz device Bit 5 of the PCI status register is supported and shows PCI 6152 66BC as a 66 MHz capable device to the system PCI 6152 66BC does not have an M66EN pin...

Страница 77: ...inputs set to 0 17 1 1 Auto Mode EEPROM Access Using auto mode the PCI 6152 can access the EEPROM on a word basis via hardware sequencer User need only to access word data via PCI 6152 configuration...

Страница 78: ...time It is important to note that in the data phase bit orders are reverse of that of the address phase PCI 6152 only supports EEPROM Device Address 0 A C K M S B M S B L S B L S B S T O P Data n Dat...

Страница 79: ...set 11h 1111 autoload all EEPROM loadable registers Other combinations are undefined 03h Secondary Clock Enable Bit0 1 disable SCLKO 0 output Bit1 1 disable SCLKO 1 output Bit2 1 disable SCLKO 2 outpu...

Страница 80: ...r at offset C5h 17 3 Vital Product Data PCI 6152 contains the VPD registers as specified in the PCI Local Bus Specification Revision 2 2 The VPD information is stored in the EEPROM device along with t...

Страница 81: ...n removed from the PCI 6152 A power up reset must be performed to bring the PCI 6152 to D0 D0 D3hot If enabled to do so by the BPCCE pin the PCI 6152 will disable the secondary clocks and drive them l...

Страница 82: ...n to be asserted to indicate successful insertion It will signal the host by asserting ENUM_L The host reads register 92h to determine if ENUM_L was asserted as a result of a card insertion The host w...

Страница 83: ...20 Package Specifications 20 1 160 pin Tiny BGA This specification outlines the mechanical dimensions for 160 pin Tiny BGA package as shown below All dimensions are in millimeters mm SIDE VIEW BOTTOM...

Страница 84: ...l Dimension Minimum Nominal Maximum e Ball pitch 1 00 A Overall package height 1 40 A1 Package standoff height 0 27 A2 Encapsulation thickness 0 70 b Ball diameter 0 35 0 40 0 45 C Substrate thickness...

Страница 85: ...LX Technology Inc All rights reserved 85 20 2 160 pin Standard PQFP This specification outlines the mechanical dimensions for 160 pin standard PQFP plastic quad flat pack package as shown below All di...

Страница 86: ...n PQFP package dimensions Millimeters Symbol Min Nom Max A 4 45 A1 0 35 0 45 0 65 A2 3 4 3 6 3 8 b 0 2 0 3 0 4 c 0 10 0 15 0 25 D 31 6 32 0 32 4 D1 27 8 28 0 28 2 E 31 6 32 0 32 4 E1 27 8 28 0 28 2 e...

Страница 87: ...ins 5 5V Maximum Power 300mW Note Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device This is a stress rating only and functional operation of the device...

Страница 88: ...O pin Interface I O Voltage 3 0 5 5 V Vih Input HIGH Voltage 0 5 VDD VIO V Vil Input LOW Voltage 0 5 0 3 VDD V Vol Output LOW Voltage Iiout 1500 A 0 1 VDD V Vol5V 5V Signalling Output LOW Voltage Iiou...

Страница 89: ...ocks Vt3 0 8V for 5V clocks 0 3VCC for 3 3V clocks 21 4 1 33 MHz PCI Clock Signal AC parameters Symbol Parameter Minimum Maximum Unit Tcyc PCLK SCLK cycle time 30 ns Thigh PCLK SCLK high time 11 ns Tl...

Страница 90: ...nimum Maximum Unit Tcyc PCLK SCLK cycle time 15 30 ns Thigh PCLK SCLK high time 6 ns Tlow PCLK SCLK low time 6 ns PCLK SCLK slew rate 1 5 4 V ns Tsclk Delay from PCLK to SCLK 0 5 ns Tsclkr PCLK rising...

Страница 91: ...su Input setup time to CLK bused signals 7 ns Tsu ptp Input setup time to CLK point to point 10 12 Th Input signal hold time from CLK 0 ns 21 5 2 66 MHz PCI Signal Timing Symbol Parameter Minimum Maxi...

Страница 92: ...SEL_L VDD S_TRDY_L S_IRDY_L S_FRAME_L VSS S_CBE_L 2 S_AD 16 VDD S_AD 17 S_AD 18 S_AD 19 VSS S_AD 20 S_AD 21 S_AD 22 VDD S_AD 23 S_CBE_L 3 S_AD 24 VSS S_AD 25 S_AD 26 VDD S_AD 27 S_AD 28 S_AD 29 VSS S_...

Страница 93: ...P 009 S_TRDY_L STS 010 S_IRDY_L STS 011 S_FRAME_L STS 012 VSS P 013 S_CBE_L 2 TS 014 S_AD 16 TS 015 VDD P 016 S_AD 17 TS 017 S_AD 18 TS 018 S_AD 19 TS 019 VSS TS 020 S_AD 20 TS 021 S_AD 21 TS 022 S_A...

Страница 94: ...TS 101 P_STOP_L STS 102 NC 103 VSS P 104 P_PERR_L STS 105 P_SERR_L OD 106 P_PAR TS 107 P_CBE_L 1 TS 108 VDD P 109 P_AD 15 TS 110 P_AD 14 TS 111 P_AD 13 TS 112 VSS P 113 P_AD 12 TS 114 P_AD 11 TS 115 P...

Страница 95: ...P_CBE_L 1 TS 095 P_CBE_L 2 STS 082 P_CBE_L 3 TS 066 P_CLK I 100 P_DEVSEL_L STS 096 P_FRAME_L STS 068 P_GNT_L I 083 P_IDSEL I 097 P_IRDY_L STS 106 P_PAR TS 104 P_PERR_L STS 069 P_REQ_L O 105 P_SERR_L O...

Страница 96: ...O 003 S_SERR_L I 006 S_STOP_L STS 009 S_TRDY_L STS 052 S_VIO I 116 VDD P 008 VDD P 015 VDD P 023 VDD P 030 VDD P 040 VDD P 046 VDD P 056 VDD P 060 VDD P 075 VDD P 080 VDD P 090 VDD P 098 VDD P 108 VDD...

Страница 97: ...e PCI lock mechanism on its secondary interface 2 49 s_cfn_l N C The s_cfn_l pin specifies whether 21152 uses internal or external arbitration PCI 6152 33PC only supports internal arbitration so will...

Страница 98: ...ORCAD Capture for Windows Ver 9 00 1153 1 POWER 7 PCI SLOT 4 FUNCTIONAL DESCRIPTION 6 C PCI 6152 DEMO BOARD PLX Technology Inc C 1 6 Wednesday February 14 2001 Title Size Document Number Rev Date Shee...

Страница 99: ...OPEN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 B1 12V B2 TCK B3 G...

Страница 100: ...SSTOP SSERR GPIO1 GOZ_L PCI 6152 VDD HSCLK2 SIDSEL0 SREQ0 SREQ3 SPCLK2 SPAR SAD20 SERR R21 10k U3 PCI 6152 B9 A9 C8 B8 A8 A7 B7 C7 B6 C6 A5 B5 C5 A4 C4 A3 F2 F1 G3 G2 G1 H1 H2 H3 J2 J3 K1 K3 L1 L2 L3...

Страница 101: ...AD6 SINTC SPERR REQ64 SAD0 SAD11 SCBE1 SAD7 SAD10 SAD24 SAD7 SAD9 12V SAD30 PCI_5V SAD10 PA3 PCIASIDE_OPEN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34...

Страница 102: ...SINTC SAD5 SAD27 PCI_5V SAD8 SPAR SAD7 SINTA SINTA 12V SAD17 3V SAD16 SAD21 SPRST SIRDY SINTC SAD28 SPCLK3 SAD1 SDEVSEL SAD9 SAD20 SAD29 SIRDY THIS IS AN UNVERIFIED EXAMPLE PLEASE CHECK FOR POSSIBLE...

Страница 103: ...X Technology Inc C 6 6 Monday February 26 2001 Title Size Document Number Rev Date Sheet of C37 1UF_E 3V PCI_3V C5 1UF_E C38 1UF_E THIS IS AN UNVERIFIED EXAMPLE PLEASE CHECK FOR POSSIBLE MISTAKES PLX...

Страница 104: ...1 device can be connected to the interface PCI 6152 66BC can provide the electrical isolation and arbitration necessary to connect more than one 66 MHz PCI device to the AGP interface Typical Applicat...

Страница 110: ...PCI 6152 Data Book v2 0 2003 PLX Technology Inc All rights reserved 110 Figure 6 Primary to Secondary Memory Write transaction followed by Secondary to Primary Memory Write transaction...

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