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Summary of Features

The table below provides a summary of features and options available in the NTx-Pro IP engine.

NTx-Pro IP Engine Feature Summary

NTx-Pro

Hardware

User Circuitry Interface

Pixel Bus

FPGA

Altera Cyclone III

EP3C40U484

Image Buffer

16-bit wide
32 MB DDR2 RAM

Persistent Memory

16-bit wide 8 MB parallel FLASH

Inputs/Outputs

GPIO Inputs

4 x 2.5V LVTTL

GPIO Outputs

4 x 2.5V LVTTL

Camera Control Outputs

4 x 3.3V LVTTL/LVCMOS

Programmable Logic Controller (PLC)

Pulse Generators (timers)

Rescaler (16-bit)

Delayer

General Purpose Counters

Input Debouncing

Yes

Timestamp Generator

Yes

Timestamp Trigger

Yes

Software Controlled I/O

Host Interrupts

Yes

Network

Gigabit Ethernet

Yes

Zero-loss packet resend

Yes

Ethernet Bandwidth

1 Gb/s

Unicast

Yes

Multicast

Yes

BOOTP

Yes

DHCP

Yes

Other Features

Serial Ports (UART)

1 x 2.5V LVTTL
1 x 3.3V LVTTL/LVCMOS

Bulk Interface (USRT, UART, I2C)

1 x 2.5V LVTTL

PHY

Broadcom BCM5461

Power Connector

2-pin, 0.100” header

Ethernet Connector

RJ45 with embedded magnetics

FPGA External Static Memory

16-bit wide 2 MB SRAM

Clock Generator

Included

Boundary Scan Chain

FPGA and PHY

Frame Grabber

Number of Data Channels

1 (Std)
Up to 4 (Opt)

Содержание iPort NTx-Pro

Страница 1: ...NTx Pro Hardware Guide...

Страница 2: ......

Страница 3: ...proven performance...

Страница 4: ...d agree to indemnify Pleora for any damages resulting from such improper use or sale Copyright 2010 Pleora Technologies Inc All information provided in this manual is believed to be accurate and relia...

Страница 5: ...FC FPC 17 Components 17 Pinout Orientation 17 2 x 50 Pin FFC FPC Layout 18 Connector Names J5 Connector Detail 18 Connector Names J4 Connector Detail 20 Signal Names J5 50 Pin FFC FPC Detail 22 Signal...

Страница 6: ...ignals 39 Output Power Signals 40 Power Consumption 41 User Circuitry Power 41 Status LEDs Overview 43 Location of LEDs 43 FPGA Configuration LED 43 Network Activity LED 44 Network Connection Speed LE...

Страница 7: ...gh one or more switches to a range of other system elements for example cameras computers displays controllers and encoders in meshed real time video networks A sophisticated on board PLC Programmable...

Страница 8: ...elow PT 01 PB 0 IP 01 32 B G NTx Pro Product Code Pleora Technologies Reserved Speed 01 1 GigE Video Interface PB Pixel Bus Protocol G GigE Vision Protocol Package B OEM Board DRAM Memory 32 32 MBytes...

Страница 9: ...PLC Pulse Generators timers 4 Rescaler 16 bit 1 Delayer 1 General Purpose Counters 1 Input Debouncing Yes Timestamp Generator Yes Timestamp Trigger Yes Software Controlled I O 4 Host Interrupts Yes N...

Страница 10: ...1 MHz Max 90 MHz Taps per Data Channel 1 2c 4 Opt b Image Width pixels d Min 8 Default 640 Max 16 376 Increment 8 Image Height pixels Min 1 Default 480 Max 16 383 Increment 1 Windowing Yes Decimation...

Страница 11: ...e J2 CONN PRT 5PN DOUBLE ROW CLP 105 02 G D Samtec NOTE Mate to Connector Summary Mate Connector Description Mfr ID Source Mfr Mate to J2 CONN HEADER 10POS DUAL 05 SMD FTSH 105 01 l DV Samtec Mate to...

Страница 12: ...rs and LEDs The figure below illustrates the location of the all connectors and LEDs for the NTx Pro board User Circuitry Connectors J4 J5 Power Connector J3 JTAG Connector J2 Ethernet Connector J1 Ne...

Страница 13: ...rammable Logic Controller PLC I Os in J4 allow the NTx Pro IP Engine to control external machinery or be controlled by external circuitry The IP Engine s PLC is versatile and programmable and the pote...

Страница 14: ...images and responds to the commands All network traffic is based on standard Ethernet protocols JTAG Connector This connector is used in conjunction with the IP Offering of the NTx Pro it serves for...

Страница 15: ...esented below Components Connector Components Part Description Part Number 5 pin double row header 0 050 1 27 mm pitch Samtec CLP 105 02 G D JTAG Header Layout The JTAG header layout indicating the JT...

Страница 16: ...ype Note 1 2 5V Power Power Output 2 GND Ground Ground 3 TDI Test Data In JTAG Test Data Input 1Kohm Pull up resistor 4 TDO Test Data Out JTAG Test Data Output 5 TMS Test Mode Select JTAG Test Mode Se...

Страница 17: ...Category 5e cables or the superior Category 6 6a cables Pleora Technologies Inc recommends unshielded twisted pair UTP cables Note that at greater distances the voltage differen tial between the grou...

Страница 19: ...below Components Connector Components Part Description Part Number 2 pin header with pins Tyco Electronics 644874 2 Mating Components Part Description Part Number 2 pin shell with sockets Molex 22 01...

Страница 21: ...ber FFC cable 50 pin 0 5 mm pitch length as required by your design Commonly available Parlex a Johnson Electric Company www parlex com 050R50 XXXXB A where XXXX is the length of 0001 to 9999 in mm Pi...

Страница 22: ...il Pin No Name Function Type Note 1 3 3V Power Power Output 3 3V from the NTx Pro 2 3 3V Power Power Output 3 3V from the NTx Pro 3 3 3V Power Power Output 3 3V from the NTx Pro 4 GND Ground Ground 5...

Страница 23: ...put Pixel data 32 IO33_20_ B33P PIXEL_DATA20 Input Pixel data 33 IO33_21 PIXEL_DATA21 Input Pixel data 34 IO33_22 PIXEL_DATA22 Input Pixel data 35 IO33_23 PIXEL_DATA23 Input Pixel data 36 GND Ground G...

Страница 24: ...IO25_2_ R13N GPIO_INPUT1 Input FPGA PLC general purpose input 13 IO25_3_ R13P GPIO_OUTPUT1 Output FPGA PLC general purpose output 14 IO25_4 GPIO_INPUT2 Input FPGA PLC general purpose input 15 IO25_5_...

Страница 25: ...8 IO25_25 Reserved High impedance Hi Z 39 IO25_26 Reserved High impedance Hi Z 40 IO25_27 Reserved High impedance Hi Z 41 IO25_28_ T30P Reserved High impedance Hi Z 42 IO25_29_ T30N Reserved Highimped...

Страница 26: ...s on these signals Both the FPGA main load and backup load have an internal weak but greater than 470K pull up enabled by default If these pins remain uncon nected the main load is selected For improv...

Страница 27: ...16V 5 to 16V 5V recommended Refer to Power Requirements on page 39 IO25_PLL_P0 7 I O 2 5V Reserved IO25_PLL_N0 8 I O 2 5V Reserved IO25_0 IO25_32 10 17 19 26 28 35 37 44 46 I O 2 5V FPGA I Os IO25_CL...

Страница 28: ...switches SW1 SW2 to select main backup load FPGA_SEL1 4 Use for pull up pull down resistors R value 1K or less 1K 2 5V 3 3V 1K SW1 R R FPGA Main Backup Load Selection Option 1 1K 2 5V 3 3V 1K SW2 R R...

Страница 32: ...UNDER 6 inches NOMINAL 0 005 inch B Dimensions OVER 6 inches add 0 001 every 1 inch C Flatness 0 015 unless specified D Hole diameters 0 002 unless specified 3 This mechanical draft illustrates only m...

Страница 33: ...h level width tCH 4 5 ns typ PIXEL_CLK low level width tCL 4 5 ns typ PIXEL_CLK frequency fCP 90 MHz PIXEL_CLK clock period tCP 11 0 ns PIXEL_DATAx setup time tDS 2 ns By design PIXEL_DATAx hold time...

Страница 34: ...I2FI tLI2FI tFV2FI tFV2FV tLLI2DV Case 2 FVAL and LVAL are Edge sensitive 1 0 N 1 0 tLI2LV FVAL LVAL DVAL tFV2LV tFI2FV tLV2LI 1 1 N 1 M PIXEL_DATAx 0 0 N 0 0 0 1 0 0 1 N M Don t Care Window Size N x...

Страница 35: ...L and LVAL is high when they re set as level high sensitive or rising edge sensitive Their valid state is low when they re set as level low sensitive or falling edge sensitive b If LVAL is valid befor...

Страница 37: ...with the following exceptions The Bulk Interface uses the BULK0_RXD in place of UART1_RXD and BULK0_TXD in place of UART1_TXD Bulk Interface USRT The USRT universal synchronous receiver transmitter s...

Страница 38: ...tHRX 0 ns 44 ns SCK TXD TXD0 TXD1 TXD2 TXD3 TXD4 RXD START TXD5 TXD6 TXD7 STOP RXD0 RXD1 RXD2 RXD3 RXD4 START RXD5 RXD6 RXD7 TXD3 TXD2 TXD4 RXD2 STOP tDTX tSCK tSRX RXD4 tHRX RXD3 SCK TXD RXD 34 Seri...

Страница 39: ...user circuitry Read and Write Methods Read and write methods using the I2C protocol with the eBUS SDK are explained below eBUS SDK Suite The eBUS SDK Suite includes a PvIPEngineI2CBus class that allo...

Страница 41: ...following signals UARTx_TXD UARTx_RXD DGND return Timing for UART The NTx Pro IP Engine supports these UART protocols 8 bit data transfer 1 start bit Any parity even odd or none 1 or 2 stop bits UART...

Страница 43: ...ctor Max 0 4A per pin x3 3 3V The power generation scheme of the NTx Pro is shown in the figure below Input Power Signals The section determines the input current requirements The table below contains...

Страница 44: ...V 0 4A 2 5V is generated by a switcher connected to FILTER_VIN 2 5V is available for user circuitry through the J4 connector Current per pin is 0 4A Maximum current sink by user circuitry through all...

Страница 45: ...mption of the NTx Pro IP Engine with main load version 2 2 9 Power consumption will vary with the FPGA main load version All measurements are 50 mW 12V 0 15A 1 80W No Streaming 12V 0 17A 1 98W Streami...

Страница 47: ...s and Component IDs LED Component ID Power LED D2 Network activity LED J1 Network connection speed J1 FPGA Programming LED D2 Network Connection Speed LED J1 Network Activity LED J1 Power and Firmware...

Страница 48: ...k Green on blinking Data is being transmitted or received Network Connection Speed LED Network Connection Speed LED LED Action Off No connection 10 Mbps connection or 100 Mbps con nection Green on 1 G...

Страница 49: ...EL_DATA5 Port A5 A5 A5 A5 A5 A5 R5 PIXEL_DATA6 Port A6 A6 A6 A6 A6 A6 R6 PIXEL_DATA7 Port A7 A7 A7 A7 A7 A7 R7 PIXEL_DATA8 Port B0 B0 A8 A8 A8 A8 G0 PIXEL_DATA9 Port B1 B1 A9 A9 A9 A9 G1 PIXEL_DATA10...

Страница 50: ...k Pixel Bus Definitions Copyright 2010 Pleora Technologies Inc YUV Color Bit Assignments You can inquire about YUV Color Bit Assignments for the NTx Pro IP Engine by contacting Pleora Technologies Inc...

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